A semiconductor device according to one aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and extends in a direction forming an angle of 30 to 30 with respect to the first direction. A semiconductor device according to another aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and has a joint portion that is long in one direction in plan view and an angle of a long direction of the joint portion with respect to the first direction is 30 to 30.

A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.

An amplifier circuit that includes an RF amplifier; an impedance matching network; a higher order harmonic termination circuit; a fundamental frequency matching circuit; and an integrated passive device (IPD) that includes a silicon carbide (SiC) substrate. The integrated passive device (IPD) includes one or more reactive components of the fundamental frequency matching circuit and one or more reactive components of the higher order harmonic termination circuit.

According to one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies includes a plurality of semiconductor chips. The method further includes forming a plurality of first wires on the stacked bodies. The first wires connecting the stacked bodies to each other. The method further includes forming a resin layer on the stacked bodies and the first wires, then thinning he resin layer until the first wires are exposed.

A semiconductor device according to some embodiments includes a semiconductor die, and a bond pad on a first side of the semiconductor die for receiving a wire bond. The bond pad includes a discontinuous uppermost surface opposite the first side of the semiconductor die.

A semiconductor package includes: a package substrate including a first substrate region and a second substrate region, wherein the first substrate region at least partially surrounds the second substrate region; a semiconductor chip disposed on the package substrate; a mold provided on the package substrate and covering the semiconductor chip; and a shield provided on the mold and the package substrate, wherein a thickness of the first substrate region is smaller than a thickness of the second substrate region.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.