Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

According to one embodiment, a semiconductor device includes a wiring substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface. A first electrode is on the first surface. A semiconductor element is on the wiring substrate and electrically connected to the first electrode. A resin layer covers the semiconductor element and the first surface from a first direction orthogonal to the first surface. A portion of the resin layer contacts the side surface of the wiring substrate from a second direction parallel to the first surface. The resin layer has an outside side surface that is substantially parallel to the first direction.

A semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die stacked on the first die and offset from it in a first direction and a second direction that are perpendicular to each other, and a third semiconductor die stacked on the first and second dies and offset from them in the first direction. The first semiconductor die includes a first pad and a second pad, arranged successively in the second direction. The second semiconductor die includes a third pad and a fourth pad, and the third semiconductor die includes a fifth pad and a sixth pad, each arranged successively in the second direction. A first conductive pattern connects the first and fifth pads, while a second conductive pattern connects the second, fourth, and sixth pads. The first and second conductive patterns are spaced apart from the third pad.

In a copper alloy bonding wire for semiconductor devices, the bonding longevity of a ball bonded part under high-temperature and high-humidity environments is improved. The copper alloy bonding wire for semiconductor devices includes in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir, and Pt (first element), with the balance Cu and inevitable impurities. The inclusion of a predetermined amount of the first element suppresses production of an intermetallic compound susceptible to corrosion under high-temperature and high-humidity environments at the wire bonding interface and improves the bonding longevity of a ball bonded part.

A semiconductor package includes: a package substrate including a first surface and a second surface opposite each other; at least one signal pad arranged in a first direction, at least one ground pad spaced apart from the at least one signal pad in a second direction; and a semiconductor chip on the package substrate, the semiconductor chip including at least one first pad and at least one second pad. The package substrate includes at least one signal line connected to the at least one signal pad; and a at least one ground line connected to the at least one ground pad, in which the at least one ground line extends between the at least one signal pad and the at least one ground pad in the first direction, and in which the at least one second pad is connected to the at least one ground pad through a second bonding wire.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

A fan-out stacked semiconductor package structure and a packaging method thereof are disclosed. The structure includes a three-dimensional memory chip package unit and a two-dimensional fan-out peripheral circuit chip SiP package unit. The three-dimensional memory chip package unit includes: at least two memory chips laminated in a stepped configuration; a first rewiring layer; wire bonding structures, each of which being electrically connected to the bonding pad and the first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The two-dimensional fan-out peripheral circuit chip SiP package unit includes: a second rewiring layer; at least one peripheral circuit chip; a third rewiring layer, bonded to the peripheral circuit chip; metal connection pillars; a second encapsulating layer, encapsulating the peripheral circuit chip and the metal connection pillars; and second metal bumps, formed on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

The semiconductor module includes a first device that has an IGBT and a second device that has a reflux diode which is anti-parallel connected to the IGBT, which has a forward threshold voltage less than a reverse withstand voltage of the IGBT, and which has a forward breakdown voltage in excess of the reverse withstand voltage of the IGBT.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.