An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.

A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.

A method of fabricating a pixel array substrate includes forming a semiconductor layer on a substrate, forming a metal layer stack on the semiconductor layer, forming a photoresist pattern on the metal layer stack, and removing part of the metal layer stack and the semiconductor layer not covered by the photoresist pattern at one time using a dry etching process to form a source, a drain, and a semiconductor pattern of an active device. The metal layer stack includes a first titanium layer, an aluminum layer, and a second titanium layer. The semiconductor pattern has a groove located between the source and the drain. The source and the drain respectively have a source edge and a drain edge opposite to each other, which defines two opposite side walls of the groove respectively. A pixel array substrate produced by using the method of fabricating the pixel array substrate is also disclosed.

A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.

A cleaning solution includes a solvent having Hansen solubility parameters: 25>.sub.d>13, 25>.sub.p>3, 30>.sub.h>4; an acid having an acid dissociation constant pKa: 11<pKa<4, or a base having pKa of 40>pKa>9.5; and a surfactant. The surfactant is an ionic or non-ionic surfactant, selected from ##STR00001##
R is substituted or unsubstituted aliphatic, alicyclic, or aromatic group, and non-ionic surfactant has A-X or A-X-A-X structure, where A is unsubstituted or substituted with oxygen or halogen, branched or unbranched, cyclic or non-cyclic, saturated C2-C100 aliphatic or aromatic group, X includes polar functional groups selected from OH, O, S, P, P(O.sub.2), C(O)SH, C(O)OH, C(O)OR, O, N, C(O) NH, SO.sub.2OH, SO.sub.2SH, SOH, SO.sub.2, CO, CN, SO, CON, NH, SO.sub.3NH, and SO.sub.2NH.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer, a source region disposed in the semiconductor layer, a drain region disposed in the semiconductor layer, an insulating layer disposed in the semiconductor layer between the source region and the drain region, and a gate disposed over the semiconductor layer between the source region and the drain region, the gate covering a portion of the insulating layer. The insulating layer has a first sidewall extending toward the source region and a second sidewall extending toward the drain region, the first sidewall having a first slope and the second sidewall having a second slope greater than the first slope.

A semiconductor device includes an electrostatic discharge (ESD) protection device that includes an active gate structure and a plurality of dummy gate structures between the active gate structure and a source/drain region if the ESD protection device. The dummy gate structures are used as a self-aligned implant mask when forming the source/drain region. The dummy gate structures enable the source/drain region to be formed as a plurality of implant segments that are spaced apart in a substrate of the semiconductor device. The space between the implant segments provides areas in the substrate in which dopants from the implant segments may diffuse from subsequent manufacturing operations for the semiconductor device. Thus, the dopants diffuse into the substrate across a greater area of the substrate than if the source/drain region were a continuous implant region, reducing the dopant concentration from the implant segments in the substrate.

A semiconductor device includes an annular semiconductor fin over a semiconductor substrate, a first bottom source/drain structure within the annular semiconductor fin, a second bottom source/drain structure surrounding the annular semiconductor fin, a first silicide layer, a second silicide layer, a first gate structure, a second gate structure, a top source/drain structure, and a contact structure over the top source/drain structure. The first silicide layer and the second silicide layer are over the first bottom source/drain structure and the bottom second source/drain structure, respectively. The first gate structure and the second gate structure are over the first silicide layer and the second silicide layer, respectively. The contact structure includes a lower contact, a middle contact over the lower contact, and an upper contact over the middle contact. A width of the upper contact is greater than a width of the middle contact.

A method includes forming a first electrode layer having a first opening, with the first opening having a first lateral dimension, forming a first capacitor insulator over the first electrode layer, and forming a second electrode layer over the first capacitor insulator, with the second electrode layer having a second opening. The first opening is directly underlying the second opening. The second opening has a second lateral dimension greater than the first lateral dimension. The method further includes depositing a dielectric layer over the second electrode layer, and forming a contact opening, which comprises a first portion including the first opening, and a second portion including the second opening. A conductive plug is formed in the contact opening.

An etching method includes: providing a substrate having a film and a patterned mask on the film; forming a silicon-containing layer including silicon, carbon, and nitrogen on the substrate using a precursor gas containing silicon; and performing a plasma etching on the film. The substrate is placed under a depressurized environment for a time period from a start time point of the step of forming the silicon-containing layer on the substrate to an end time point of the step of performing the plasma etching on the film.