The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

A power semiconductor device includes a semiconductor structure comprising an active region, and a plurality of stress relief trenches in the semiconductor structure laterally between the active region and at least one edge of the semiconductor structure. The stress relief trenches respectively comprise opposing sidewalls and a dielectric material and/or a semiconductor material therebetween, and do not contribute to electrical conduction between first and second terminals of the power semiconductor device. Related devices and fabrication methods are also discussed.

The present disclosure provides a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Fe.sup.+3 ions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described.

A method of fabricating a semiconductor device includes forming a first shallow trench isolation structure in a first region of a substrate and second shallow trench isolation structures in a second region of the substrate. The method also includes forming a mask layer over the substrate, the first shallow trench isolation structure, and the second shallow trench isolation structures. The method further includes etching the mask layer and second shallow trench isolation structures in the second region sequentially to form a semiconductor protrusion between the second shallow trench isolation structures.

A method of protecting an edge region of a substrate includes receiving a substrate into a processing chamber. The substrate includes an exposed silicon-containing edge region (e.g., a bevel region of a wafer substrate) surrounding an interior region underlying a resist layer. The method further includes treating the exposed silicon-containing edge region and the resist layer with a metal halide precursor (such as a tungsten halide) to selectively convert the exposed silicon-containing edge region to a metal-containing protective layer (e.g., including a metal silicide such as tungsten silicide and/or a pure metal such as tungsten). The metal-containing protective layer may be configured to protect the edge region of the substrate during subsequent processing, such as an etch process during which exposed surfaces of the interior region are etched.

According to the disclosure, provided is an etching agent for etching a semiconductor substrate having a surface partially covered with a noble metal, the etching agent including: an oxidizing agent; hydrogen fluoride; and ammonium fluoride. 0.5n/m5.0 is satisfied, where m is a molar concentration [mol/L] of the hydrogen fluoride, and n is a molar concentration [mol/L] of the ammonium fluoride.

Provided is a method of enhancing etch resistance of a photoresist pattern, the method including forming a photoresist film including a photoresist composition including a polymer, forming a photoresist pattern by patterning the photoresist film, and irradiating the photoresist pattern with a laser, wherein the etch resistance of the photoresist pattern irradiated with the laser is enhanced.

Methods and related systems for forming an EUV-sensitive layer. The methods comprise executing a plurality of deposition cycles. A deposition cycle comprises a first precursor pulse and a second precursor pulse. The first precursor pulse comprises exposing the substrate to a first precursor. The first precursor comprises two or more acyl halide functional groups. The second precursor pulse comprises exposing the substrate to a second precursor. In some embodiments, the second precursor comprises two or more hydroxyl functional groups.