A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.

An etching method includes: (a) providing a substrate including an etching target film and a mask on the etching target film; (b) after (a), forming a metal-containing deposit on the mask by a first plasma generated from a first processing gas including a metal-containing gas and a hydrogen-containing gas; (c) after (b), deforming or modifying the metal-containing deposit by a second plasma generated from a second processing gas different from the first processing gas; and (d) after (c), etching the etching target film.

A method for etching a layer includes loading a substrate onto a substrate holder disposed within a processing chamber, the substrate including a carbon-containing layer and a patterned mask layer; cooling the substrate holder to a first temperature between 150 C. and 40 C.; and while maintaining the first temperature of the substrate holder, patterning the carbon-containing layer to form a channel in the carbon-containing layer, the patterning including simultaneously flowing into the processing chamber an etching gas including oxygen and a passivating gas including silicon and fluorine; and generating a plasma within the processing chamber.

A method includes forming a complementary field-effect transistor comprising forming a lower source/drain region, and forming an upper source/drain region over the lower source/drain region. An etching process is performed to etch-through the upper source/drain region and to form a contact opening. The etching process is stopped on a top surface of the lower source/drain region. The method further includes forming a dielectric contact spacer in the contact opening, forming a first silicide layer over the lower source/drain region, forming a contact plug over and contacting the first silicide layer, and forming a second silicide layer underlying and contacting a bottom surface of the lower source/drain region.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a semiconductor substrate. The semiconductor substrate includes a base portion, a semiconductor bar portion on a first active area of the base portion, a set of semiconductor branch portions extending from a sidewall of the semiconductor bar portion to a second active area of the base portion, and first and second isolation structures formed on the second active area of the base portion. The first interface between the first isolation structure and the semiconductor bar portion is flat. The second interface between the second isolation structure and the semiconductor bar portion is flat. The first interface and the second interface are staggered from each other along the extending direction of the semiconductor bar portion.

A method for plasma etching in a plasma processing chamber, where the method includes providing a substrate having a silicon-based semiconductor layer disposed over an etch stop layer and a patterned masking layer disposed over the silicon-based semiconductor layer, the patterned masking layer exposing a surface of the silicon-based semiconductor layer; using the patterned masking layer as an etch mask, vertically etching the silicon-based semiconductor layer using a first plasma etch process to form a pattern of lines and expose portions of the underlying etch stop layer, one or more lines of the pattern of lines having a foot along its base, the first plasma etch process including generating a first plasma; and vertically etching in situ the pattern of lines using a second plasma etch process, the second plasma etch process including generating a second plasma from a first gas including chlorine and a second gas including a compound of hydrogen with Si, Br, I, P, or S, the second plasma being different from the first plasma, and exposing the pattern of lines to the second plasma to remove the foot from the pattern of lines.

Provided is an etching solution composition that can have both a higher etch selectivity of silicon nitride and a reduction in the deposition of silica on the surface of silicon oxide. An inorganic acid-based etching solution composition for selectively etching away silicon nitride from a semiconductor containing silicon nitride and silicon oxide, the etching solution composition comprising: (a) an etch inhibitor that reduces etching of silicon oxide; and (b) a deposition inhibitor that reduces deposition of silica on a surface of silicon oxide.

A process for manufacturing electroacoustic modules including: forming an assembly with a redistribution structure and a plurality of dice arranged in a dielectric region; forming a wafer with a semiconductor body and a plurality of respective unit portions laterally staggered, each of which includes a respective supporting region, set in contact with the semiconductor body, and a number of actuators; reducing the thickness of the semiconductor body and then selectively removing portions of the semiconductor body so as to singulate, starting from the wafer, a plurality of transduction structures, each including a semiconductor substrate, which contacts a corresponding supporting region and is traversed by cavities delimited by portions of the supporting region that form membranes mechanically coupled to the actuators; and then coupling the transduction structures to the redistribution structure of the assembly.

A semiconductor device and method of making is described. A substrate (1) topped by a buffer layer (2) of a first conductivity type and one or more epitaxial layers (3) of the same type. In the topmost epitaxial layer, a body region (4) of a second conductivity type is formed, along with a source region (5) of the first conductivity type. Beneath the source region lies a buried body contact region (6) of the second conductivity type. A trench (16) in the source region provides access to the body contact region and is narrower than it. Ohmic contacts include a source contact (9) overlapping the source region on trench sidewalls and a body contact (10) overlapping the body contact region at the trench bottom. Between body regions of neighboring cells, a JFET region (13) is formed.

An etchant composition offers an etch rate on silicon which is sensitive to a dopant type of the silicon. The etchant composition comprises a base and an additive distinct from the base. The additive has between one and six carbon atoms per molecule.