A semiconductor chip includes a semiconductor substrate that includes a front side and a back side that are opposite to each other, a circuit structure disposed on the front side of the semiconductor substrate, a first through via that penetrates the semiconductor substrate in a vertical direction perpendicular to the front side of the semiconductor substrate and is electrically connected to the circuit structure, and a dummy via buried in the semiconductor substrate, wherein a lower end of the dummy via is spaced apart from the back side of the semiconductor substrate.

A FET channel includes a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also includes a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.

A manufacturing method of a semiconductor device includes depositing a first bilayer structure over a substrate, in which the first bilayer structure includes a silicon oxide layer and a silicon nitride layer over the silicon nitride layer; forming a first carbonaceous hard mask on the first bilayer structure; forming a second bilayer structure on the first carbonaceous hard mask; forming a mask stack of alternating anti-reflecting coating (ARC) hard masks and second carbonaceous hard masks on the second bilayer structure; and coating a photoresist on the mask stack.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.

Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

Provided is a method for manufacturing a semiconductor device including performing optical proximity correction on a layout. The optical proximity correction includes generating a contour of a target pattern of the layout, generating first to fourth error vectors between the contour and first to fourth edge segments of the target pattern, and generating a correction pattern by sequentially performing a first correction and a second correction on the target pattern. The first correction includes moving the first edge segment on the basis of the first error vector, and moving the second edge segment on the basis of the second error vector. The second correction includes moving the third and fourth edge segments on the basis of a sum of the third error vector and the fourth error vector. The first and second edge segments face each other, and the third and fourth edge segment face each other.

A method includes providing a structure in a chamber, wherein the structure comprising a first layer disposed over a substrate and a second layer disposed over the first layer; forming a mask over the structure, wherein the mask includes a plurality of protruding structures defining a plurality of openings, respectively; etching, through the mask, one or more portions of the second layer using a first gas to expose one or more portions of the first layer; based on a second gas, forming a plurality of cap structures covering upper portions of the protruding structures, respectively, and etching, through the mask with the cap structures, the one or more exposed portions of the first layer; and etching, through the mask, one or more portions of another second layer disposed below the first layer using the first gas.

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask.

A method for manufacturing semiconductor devices is disclosed. The method includes providing, in a chamber, a substate covered by a patterned mask. The method includes applying, in the chamber, radiation locally on a portion of the substate that is not covered by the patterned mask. The method includes etching, in the chamber, the portion of the substate through a dry etching process.