The first semiconductor layer includes a first region positioned between field plate electrodes adjacent to each other in the first direction, a second region positioned between field plate electrodes adjacent to each other in the second direction, and a third region positioned between field plate electrodes adjacent to each other with an intersection part interposed, the intersection part being between the gate electrode extending in the first direction and the gate electrode extending in the second direction. A first-conductivity-type impurity concentration of the first region and a first-conductivity-type impurity concentration of the second region are greater than a first-conductivity-type impurity concentration of the third region.

Disclosed is a split-gate power MOS device and a manufacturing method thereof. The method comprises: forming a trench in an epitaxial layer on a substrate; forming a first insulation layer on a surface of the epitaxial layer and in the trench; filling a cavity with polycrystalline silicon, performing back-etching; performing spin-coating on the first gate conductor layer to form a second insulation layer; forming a mask on the second insulation layer, removing a portion of the first insulation layer, to expose an upper portion of the trench; forming a gate oxide layer on a sidewall of the upper portion of the trench and the surface of the epitaxial layer; and forming a second gate conductor layer in the upper portion of the trench. According to the present disclosure, voltage withstand and electric leakage between the first gate conductor layer and the second gate conductor layer are reduced.

A new design of a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and method of manufacturing the MOSFET are disclosed. The SiC MOSFET features a trench formed in SiC layers that includes a buried p-well region near the bottom of the trench that extends along a sidewall of the trench. The SiC MOSFET may also include a p-body and built-in channel on an opposite sides of the trench. The SiC MOSFET configurations may help prevent dielectric breakdown and bipolar degradation in the SiC.

A semiconductor device includes: a trench gate structure extending from a first surface into a silicon carbide semiconductor body along a vertical direction; and a body region of a first conductivity type adjoining a sidewall of the trench gate structure along a first lateral direction. The body region includes a first body sub-region adjoining the sidewall, a second body sub-region adjoining the sidewall, and a third body sub-region. The second body sub-region is arranged, along the first lateral direction, between the third body sub-region and the sidewall. An average net doping concentration along the first lateral direction is larger in the third body sub-region than in the second body sub-region. A degree of partial compensation of dopants of the first conductivity type by dopants of a second conductivity type is larger in the second body sub-region than in the third body sub-region.

According to one embodiment, an ion implantation device includes an ion beam irradiation unit that emits an ion beam; a target substrate holding unit that holds a target substrate disposed in a path of the ion beam; a first mask holding unit that holds a first mask disposed in front of the target substrate in the path; and a second mask holding unit that holds a second mask disposed between the first mask and the target substrate in the path. The first mask includes a first opening pattern through which the ion beam is able to pass. The second mask includes a second opening pattern through which the ion beam is able to pass.

The present invention uses the thinned second pad oxide layer as the pad oxide layer for the subsequent shallow trench isolation process. Therefore, it is not necessary to remove the entire pad oxide layer on the substrate surface after the P-type high-voltage ion well thermal drive-in process. The subsequent step of re-growing the pad oxide layer is omitted, thereby simplifying the process complexity.

The present invention uses the thinned second pad oxide layer as the pad oxide layer for the subsequent shallow trench isolation process. Therefore, it is not necessary to remove the entire pad oxide layer on the substrate surface after the P-type high-voltage ion well thermal drive-in process. The subsequent step of re-growing the pad oxide layer is omitted, thereby simplifying the process complexity.

A device includes a substrate, a gate structure, a source/drain region, a first silicide layer, a second silicide layer and a contact. The gate structure wraps around at least one vertical stack of nanostructure channels. The source/drain region abuts the gate structure. The first silicide layer includes a first metal component on the source/drain region. The second silicide layer includes a second metal component different than the first metal component, and is on the first silicide layer. The contact is on the second silicide layer.

A semiconductor device includes a substrate, an epitaxial layer on the substrate, a well region in the epitaxial layer, an insulating pillar extending into the epitaxial layer, a first doping region in the epitaxial layer and surrounding the insulating pillar, a second doping region under the first doping region, and a gate structure formed at one lateral side of the insulating pillar and extending into the epitaxial layer. The substrate and the epitaxial layer each have a first conductivity type. The well region and the first and second doping regions each have a second conductivity type. The gate structure is separated from the insulating pillar. The insulating pillar penetrates the first doping region by extending from the top portion to the bottom portion of the first doping region. The first doping region is electrically connected to the well region.

A semiconductor device includes a substrate, an epitaxial layer on the substrate, a well region in the epitaxial layer, an insulating pillar extending into the epitaxial layer, a first doping region in the epitaxial layer and surrounding the insulating pillar, a second doping region under the first doping region, and a gate structure formed at one lateral side of the insulating pillar and extending into the epitaxial layer. The substrate and the epitaxial layer each have a first conductivity type. The well region and the first and second doping regions each have a second conductivity type. The gate structure is separated from the insulating pillar. The insulating pillar penetrates the first doping region by extending from the top portion to the bottom portion of the first doping region. The first doping region is electrically connected to the well region.