Patent classifications
H10P14/418
Tungsten defluorination by high pressure treatment
An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.
Deposition method and deposition apparatus
A film deposition method includes preparing a substrate having an insulating film formed thereon, forming a seed layer on the insulating film, and supplying a molybdenum-containing gas and a reducing gas to the substrate having the seed layer famed thereon, to foam a molybdenum film on the seed layer.
Mid-valent molybdenum complexes for thin film deposition
Described herein are IC devices that include molybdenum or a molybdenum compound, such as compounds including oxygen or nitrogen. The molybdenum may be deposited at a high concentration, e.g., at least 50% atomic density. Also described herein are mid-valent molybdenum precursors for depositing molybdenum, and reactions for producing the mid-valent molybdenum precursors. For example, the molybdenum precursors may be generated by reacting a higher-valent molybdenum compound with an amidinate or a formamidinate.
Non-metal incorporation in molybdenum on dielectric surfaces
Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.
METHOD FOR PRODUCING STRUCTURED METAL CONTACTS ON A SEMICONDUCTOR SUBSTRATE
In a method for producing structured metallic contacts on a semiconductor substrate, in one embodiment a layer sequence consisting of multiple metallic contact materials is deposited on the entire surface of the semiconductor substrate, and a further metallic contact material is applied on the layer sequence in predetermined contact regions. Then, the layer sequence in the contact regions undergoes a thermal treatment to form a low impedance contact from a Schottky contact. The thermal treatment is carried out by scanning the layer sequence with a laser beam. In the method, the wavelength of the laser beam, the metallic contact material of the topmost layer of the layer sequence and the further metallic contact material are tuned to each other in such a way that the metallic contact material of the topmost layer of the layer sequence has a reflectivity for the laser beam that is 1.3 times higher than that of the further metallic contact material. This results in a self-adjusting thermal treatment without the need for an additional protective mask.
Thin film deposition method and manufacturing method of electronic device applying the same
A thin film deposition method may include preparing a substrate structure having an opening region formed in a vertical direction and a plurality of holes formed in a horizontal direction in each of two side portions exposed by the opening region, and adsorbing an inhibitor to surfaces of the substrate structure so that an adsorption density of the inhibitor outside of the plurality of holes is higher than an adsorption density inside of the plurality of holes by adsorbing the inhibitor in a deposition environment in which a gas diffusivity is larger in the vertical direction than in the horizontal direction. A deposition process of a material film on the inside and outside of the plurality of holes is then performed, wherein a deposition rate of the material film may vary according to the adsorption density of the inhibitor.
METHOD FOR SEMICONDUCTOR MANUFACTURING
A method for semiconductor manufacturing includes providing a substrate into a plasma processing chamber, forming a ruthenium layer over the substrate with a physical vapor deposition using a sputtering gas including krypton or xenon, and forming a ruthenium feature from the ruthenium layer with a subtractive process. The physical vapor deposition is performed at a substrate temperature of less than 100 C.
METHOD OF FORMING VANADIUM NITRIDE-CONTAINING LAYER AND STRUCTURE COMPRISING THE SAME
The current disclosure relates to methods of forming a vanadium nitride-containing layer. The method comprises providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber. The disclosure further relates to structures and devices comprising the vanadium nitride-containing layer.
Gate-all-around integrated circuit structures having vertically discrete source or drain structures
Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Provided is a semiconductor device, comprising: a semiconductor substrate; an interlayer dielectric film provided on the semiconductor substrate, having contact holes provided thereon, wherein the contact holes include a contact hole with a stepped portion on a sidewall; and a contact portion provided in the contact hole, wherein the contact portion has a barrier layer provided on the sidewall and a bottom surface of the contact hole, wherein the barrier layer has: a first region in direct contact with the stepped portion; and a second region in direct contact with the sidewall of the contact hole in a region different from the first region, wherein when a film thickness of a thickest portion of the first region is T and a film thickness of a thinnest portion of the second region is t, 0.3Tt0.95T is satisfied.