A method of processing a wafer includes forming a bonded wafer assembly by bonding one of opposite surfaces of a first wafer to a second wafer, the first wafer having a device region and an outer circumferential excessive region, applying a laser beam to the first wafer while positioning a focused spot of the laser beam radially inwardly from the outer circumferential edge of the first wafer, on an inclined plane that is progressively closer to the one of the opposite surfaces of the first wafer toward the outer circumferential edge, thereby forming a separation layer shaped as a side surface of a truncated cone, grinding the first wafer from the other one of the opposite surfaces thereof to thin down the first wafer to a predetermined thickness, and detecting whether or not the outer circumferential excessive region has been removed from the first wafer.

A method for operating an inspection apparatus is provided. The method includes placing a reticle over a stage; moving the stage by moving a vehicle supporting the stage on a rail; inspecting the reticle over the stage; and using a cleaning mechanism, generating a suction force nearby the rail.

The present disclosure relates to methods for estimating a cause of a defect in a semiconductor wafer. An example method includes acquiring contact model images including information of contact surfaces between manufacturing equipment and a wafer, receiving a defect image including defect information of a target wafer, generating, based on the contact model images and the defect image, partial representations of the contact model images that represent parts associated with the defect information, and determining, from the manufacturing equipment, suspicious equipment estimated to have caused the defect in the target wafer based on the defect image and the partial representations of the contact model images.

The present application discloses a method for analyzing a layout pattern density, comprising: step 1, providing layouts of a chip, and merging the layouts to form a wafer level layout, wherein the wafer level layout presents a first circle in a top view, and the layout comprises a plurality of mask layers; step 2, segmenting the first circle to form a plurality of check windows; step 3, searching for the mask layer containing the patterns having a height morphology, and combining the found mask layers into a pattern layer combination; step 4, sequentially calculating a pattern density of the pattern layer combination in each check window; and step 5, recording the pattern density in each check window on a third circle to form a wafer level pattern density distribution diagram. The present application can predict a height morphology of a top surface of a wafer related to a layout.

Provided is a substrate bonding apparatus comprising: a first holding unit for holding a first substrate; and a second holding unit for holding a second substrate, wherein the substrate bonding apparatus is configured to bond the first substrate and the second substrate by, after forming a contact region between a part of the first substrate and a part of the second substrate, expanding the contact region to form an initially bonded region and releasing the second substrate having the initially bonded region formed thereon from the second holding unit.

A contaminant detection device includes: a contact module configured to contact a wafer; a detection module on the contact module, the detector being configured to change color by reacting with a metal ion; and a sensing module configured to sense a color change of the detection module.

A system for rounded quadrilateral shape fitting that incudes obtaining a contour associated with an approximated quadrilateral shape with rounded corners of a representative pattern in a semiconductor wafer and smoothing the contour. Then, obtaining geometrical parameters associated with a contour of a reference shape and performing iteratively until a similarity criterion is met: a) converting the updated geometrical parameters generated in the current iteration to a corresponding contour of a reference shape, (b) fitting the corresponding contour of the reference shape to the smoothed contour and c) testing whether the fitted contour of the reference shape and the smoothed contour meet a similarity criterion, and, if not met, applying a numerical optimization to the updated geometrical parameters and moving to the next iteration.

A substrate processing method includes: generating edge information indicating a relationship between a circumferential position around a center of a substrate and an outer edge position of a first film in a radial direction of the substrate based on an image obtained by capturing a peripheral edge region on a front surface of the substrate; setting an exposure map indicating a relationship between the circumferential position and a set value of an exposure width in the radial direction based on the edge information; forming a second film on at least the peripheral edge region of the front surface; obtaining warpage information of the substrate after the second film is formed; setting a relationship between the circumferential position and exposure position information of the substrate in the exposure map based on the warpage information; and exposing the second film in the peripheral edge region in accordance with the exposure map.

Aspects of the present disclosure provide a wafer bonding system, which, for example, can include a wafer bonding tool configured to bond a first wafer and a second wafer to each other in accordance with a first wafer bonding recipe to produce a first post-bond wafer, a metrology tool integrated with the wafer bonding tool, and a tool controller coupled to the wafer bonding tool and the metrology tool. The metrology tool can be configured to measure a physical parameter of the first wafer. The physical parameter of the first wafer representing information relates to topographical features of the first wafer. The tool controller can have a model of a wafer bonding process. The model can include an input indicative of the physical parameter of the first wafer and configured to generate the first wafer bonding recipe based, at least in part, on the physical parameter of the first wafer.

Test systems and methods testing semiconductor package structures including an improved socket housing plate design that provides improved testing reliability and accuracy. The upper surface of the socket housing plate includes a non-planar shape, such as a stepped configuration including a plurality of different regions having different vertical elevations. The non-planar shape of the upper surface of the socket housing plate may mimic the warpage characteristics of the semiconductor package structures being tested, which may enable improved contact between the semiconductor package structure and the contact pins of the test system. This may improve the accuracy of the testing and reduce the occurrence of false reject tests.