A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.

The invention relates to a method for annealing of at least two wafers bonded via low-temperature direct bonding comprising heating the bonded wafers up to a first annealing temperature in the range of 100 C. to 500 C., preferably 150 C. to 400 C., even more preferred 150 C. to 200 C., holding the first annealing temperature in a range of 1 to 4 hours, preferably 1 to 3 hours, cooling down the bonded wafers to room temperature, re-heating the bonded wafers to a second annealing temperature in the range of 100 C. to 500 C., preferably 150 C. to 400 C., even more preferred 150 C. to 200 C., and cooling down the bonded wafers to room temperature.

A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and/or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface.

Integrated circuit structures and fabrication methods that substantially prevent or mitigate damage that plasma etching may cause to the FETs of a top integrated circuit in a 3-D integrated circuit (IC) stack. Embodiments of such IC structures include (1) use of substrate contacts (S-contacts) within the top integrated circuit, IC.sub.T, of the 3-D IC stack connected to the gates of FETs that may be damaged by plasma etching, and (2) selective retention of the substrate/handle wafer of IC.sub.T aligned and in electrical contact with such S-contacts so as to conduct plasma charge away from the gate oxide of the protected FETs. In addition, the novel integrated circuit structures provide an additional benefit by providing thermal dissipation paths (heat sinks) for the 3-D IC stack.

A wafer is processed by causing a cutting blade to cut into an outer circumferential surplus region of a first wafer from the front surface side by a predetermined thickness and executing cutting along the outer circumferential edge to form an annular step part in the outer circumferential surplus region, bonding the front surface side of the first wafer and the front surface side of a second wafer to form a bonded wafer, forming an annular modified layer by positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the first wafer to the inside of the first wafer and executing irradiation with the laser beam along the boundary between a device region and the outer circumferential surplus region from the back surface side, and grinding the back surface side of the first wafer to execute thinning to a predetermined finished thickness.

A processing method of a combined substrate in which a first substrate and a second substrate are bonded to each other is provided. A separation facilitating layer and a laser absorption layer are formed on the second substrate in this order. The substrate processing method includes forming a separation modification layer by radiating laser beam to the laser absorption layer while generating a stress in the laser absorption layer; and separating the second substrate from the first substrate along a boundary between the second substrate and the separation facilitating layer.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.

A bonding apparatus configured to bond substrates comprises a first holder configured to vacuum-exhaust a first substrate to attract and hold the first substrate on a bottom surface thereof; a second holder disposed under the first holder, and configured to vacuum-exhaust a second substrate to attract and hold the second substrate on a top surface thereof; a mover configured to move the first holder and the second holder relatively in a horizontal direction; a laser interferometer system configured to measure a position of the first holder or the second holder which is moved by the mover; a linear scale configured to measure a position of the mover; and a controller configured to control the mover based on a measurement result of the laser interferometer system and a measurement result of the liner scale.

A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.