A patterned silicon-on-insulator (SOI) wafer includes a semiconductor substrate, an insulator layer, and a semiconductor active layer sequentially stacked in a vertical direction perpendicular to a lower surface of the semiconductor substrate. The patterned SOI wafer includes a first region and a second region adjacent to the first region in a horizontal direction parallel to the lower surface of the semiconductor substrate, the first region being configured for low-power devices and the second region being configured for high-power devices. In the second region, at least a portion of the insulator layer is removed such that the semiconductor active layer is in direct contact with the semiconductor substrate.

A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A well is in the base layer, a doped region is above and coupled with the well, and the doped region is in the insulator layer. A drift region is above and coupled with the doped region, and the drift region is at least partially in the semiconductor layer. A gate stack is partially over the semiconductor layer and partially over drift region.

The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.

A semiconductor structure includes a SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer. A circuit element is disposed on the device layer and surrounded by a trench isolation region in the SOI substrate. A buried power rail is embedded in the trench isolation region and the buried oxide layer. The buried power rail is isolated from the device layer by the buried oxide layer and a trench-filling oxide in the trench isolation region.

A method for manufacturing an SOI wafer including a step of performing an adjustment to a film thickness of an SOI layer of the SOI wafer by wet etching. In the step of performing the adjustment to the film thickness of the SOI layer, a first etching step of etching a surface of the SOI layer using an SC1 solution; and a second etching step of etching the surface of the SOI layer by bringing the SOI layer into contact with ozone water to form an oxide film on the surface of the SOI layer and then bringing the formed oxide film into contact with an HF-containing aqueous solution to remove the oxide film, are performed in combination. The etchings are performed such that a removal amount of the SOI layer in the first etching step is smaller than that in the second etching step.

A semiconductor structure includes an SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer, a circuit element disposed on the device layer and surrounded by a trench isolation region in the SOI substrate; an etch stop layer disposed around the circuit element; a first dielectric layer disposed on the etch stop layer; and a buried power rail embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer. The buried power rail is isolated from the device layer through the buried oxide layer and trench-filling oxide in the trench isolation region.

A semiconductor structure includes a substrate, an epitaxial layer over the substrate, an isolation layer that is formed in the substrate or in the epitaxial layer, and a deep trench isolation that extends into the epitaxial layer and connects the isolation layer. The isolation layer is disposed in the second region of the semiconductor structure but does not extend into the first region of the semiconductor structure. The semiconductor structure further includes a first element formed in the first region and a second element formed in the second region. In addition, the substrate acts as the drain region of the first element. The second element is disposed in an isolation region that is defined by the deep trench isolation and the isolation layer.

In fabricating a semiconductor structure, a substrate is provided. A chiplet is bonded to the substrate. The chiplet includes a bulk layer and an active layer. A first blanket dielectric is formed over the chiplet and the substrate. A first portion of the first blanket dielectric over the chiplet is thinned. The first blanket dielectric is etched to expose the bulk layer without exposing the active layer. The bulk layer is removed. A second blanket dielectric is formed over the active layer and the first blanket dielectric. A second portion of the second blanket dielectric over the active layer is planarized with the first blanket dielectric. A first device is formed from the active layer.

In fabricating a semiconductor structure, a substrate is provided. A chiplet is bonded to the substrate. The chiplet includes a bulk layer and an active layer. A hardmask is formed over the chiplet. A photoresist is formed over the hardmask. A photoresist segment is removed to expose a hardmask segment. The exposed hardmask segment is removed to expose the bulk layer without exposing the active layer. The bulk layer is removed. The remainder of the photoresist is removed. A blanket dielectric is formed over the active layer and the hardmask. The blanket dielectric is planarized. A first device is formed from the active layer.

A semiconductor structure includes a substrate having a first doping type, a first conductive structure disposed within the substrate and having a bottom portion and a sidewall portion disposed over and coupled to the bottom portion, a first isolation layer disposed under the first conductive structure and within the substrate, and a semiconductor device disposed over the first conductive structure and including an oxide layer disposed over a first surface of the substrate. The first conductive structure is partially enclosed by the oxide layer and the first isolation layer, at least a portion of the semiconductor device is surrounded by the sidewall portion of the first conductive structure, and the semiconductor device is separated from the first conductive structure.