Methods of selectively depositing a low-k dielectric film are described. In one or more embodiments, the methods include exposing a substrate to a blocking compound, the substrate including a first surface and a second surface, the first surface including hydrogen-terminated silicon, the blocking compound selectively depositing on the first surface to form a blocked first surface; and selectively depositing the low-k dielectric film on the second surface. Methods of forming an inner spacer layer are described. In one or more embodiments, the methods include pretreating a substrate to remove oxide from a hydrogen-terminated silicon (Si) channel of the substrate, the substrate including the hydrogen-terminated silicon channel and a silicon germanium (SiGe) surface; exposing the substrate to a blocking compound, the blocking compound selectively depositing on the hydrogen-terminated silicon (Si) channel to form a blocked silicon channel; and depositing the inner spacer layer selectively on the silicon germanium surface.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first member. The second electrode includes first and second electrode regions. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial region. The second semiconductor region includes first to third semiconductor portions. At least a part of the third semiconductor portion is between the first semiconductor region and the second electrode region. The second semiconductor portion is between the first semiconductor portion and the third semiconductor region. The first member includes first and second regions.

A memory structure including a storage transistor having a data storage storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor being configurable to have a threshold voltage that is representative of data stored in the data storage region; a word line electrically connected to the gate terminal, configured to provide a control voltage during a read operation; a bit line electrically connecting the first drain or source terminal to data detection circuitry; and a source line electrically connected to the second drain or source terminal, configured to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

A substrate processing method using a substrate processing apparatus which comprises a process chamber in which a reaction space is formed to process a substrate in which a composite layer pattern having a plurality of first insulating layers and a plurality of second insulating layers alternately stacked thereon is formed, a substrate support unit, a gas distribution unit, and a plasma reactor, the method comprising the steps of: heating the substrate support unit and the gas distribution unit such that a temperature of the gas distribution unit is maintained equal to or lower than a temperature of the substrate support unit; supplying a reactive gas including a halogen-containing gas to the plasma reactor; generating radicals by applying power to the plasma reactor to activate the halogen-containing gas; and at least partially etching the plurality of first insulating layers in a lateral direction selectively with respect to the plurality of second insulating layers by supplying the radicals onto the substrate mounted on the substrate support unit through the gas distribution unit.

The present invention provides a method for forming self-transformed support plates in shallow trench isolation for advanced semiconductor devices, in which after a photolithography process to define active areas on a silicon substrate, an additional photomask is implemented to add a support plate patterning layer in areas where silicon will be etched during a STI etching step to form STI trenches. Tiny silicon support plates inside the STI trenches are formed after the silicon etching. These silicon support plates may provide mechanical support to hold neighboring patterned strips where the active areas are defined or neighboring active areas islands, and preventing them from bending, deformed or shifting. An alignment of photomask pattern at following photolithography process is eased.

Apparatus and methods related to forming films on sidewalls of memory cell stacks in memory and logic devices. In one approach, a silicon wafer is held in a chamber of an atomic layer deposition (ALD) reactor. A temperature in the reactor is controlled to a first temperature (e.g., room temperature or below) where a first gas reactant that is provided into the chamber condenses and is adsorbed on the target wafer or substrate. The first reactant or precursor is partly vaporized at a second temperature in the reactor that is greater than the first temperature. A second gas reactant is provided into the chamber. The second gas reactant reacts with the adsorbed portion of the first gas reactant in its activated state. The reaction product is a film on the sidewall of a memory cell stack or logic devices. The foregoing steps are repeated to form a desired thickness of the film.

A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO.sub.2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A method for depositing a film includes conducting electron-enhanced chemical vapor deposition with at least one hydride precursor, at least one reactive background gas, and electrons to deposit a film on a substrate with a positive substrate voltage. In an embodiment, the method is a method for depositing a silicon film, including conducting electron-enhanced chemical vapor deposition with at least one Si precursor, at least one reactive background gas, and electrons to deposit a silicon film on a substrate with a positive substrate voltage. In the embodiment, the at least one Si precursor can include Si.sub.2H.sub.6 and the at least one reactive background gas can include H.sub.2.