Disclosed is a method for manufacturing a zeroth interlayer dielectric, including: step 1: providing a semiconductor substrate subjected to a process of forming a contact etch stop layer; step 2: performing a first deposition process using a HARP process, to form a first oxide layer fully filling a spacing region; step 3: polishing the first oxide layer using a first chemical mechanical polishing process; step 4: performing wet etch to lower a top surface of the first oxide layer and form a first groove at the top of the spacing region; step 5: performing a second deposition process using an HDP CVD process, to form a second oxide layer fully filling the first groove; and step 6: polishing the second oxide layer using a second chemical mechanical polishing process, which is stopped on a surface of a first gate material layer of a first gate structure.

There is provided a technique including: at least one pipe heater configured to heat at least one gas pipe configured to supply a gas to a process chamber in which a substrate is processed; at least one temperature detector configured to detect a temperature of the at least one gas pipe; at least one temperature controller configured to be capable of, based on the temperature detected by the at least one temperature detector, outputting a manipulated variable indicating electric power to be supplied to the at least one pipe heater, and controlling the temperature of the at least one gas pipe to approach at least one desired setpoint; and a host controller configured to be capable of controlling start and stop of heating of the at least one gas pipe performed under the control of the at least one temperature controller.

A film forming method includes: a supply operation of supplying a processing gas into a processing container in which a substrate is accommodated, the processing gas including a silicon-containing gas, a nitrogen-containing gas, and a diluent gas; and a film forming operation of plasmarizing the processing gas by supplying, into the processing container, power obtained by phase-controlling and superimposing first power with a first frequency in a VHF band and second power with a second frequency different from the first frequency in the VHF band, and forming a silicon nitride film on the substrate by the plasmarized processing gas.

Provided are methods and structures for keeping the integrity of layers deposited on a semiconductor wafer through a thermal cycle. Deposition of a second backside layer, or a cap, with an internal stress opposite to a first backside layer may be used to reduce bow shift of a wafer during a thermal cycle. The first backside layer may have a tensile internal stress or a compressive internal stress. The second backside layer has an internal stress opposite to the first backside layer. Each of the backside layers may be deposited by a backside deposition apparatus.

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*10.sup.10 cm.sup.2 eV.sup.1 to 1.2*10.sup.10 cm.sup.2 eV.sup.1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.

There is provided a technique that includes: forming a nitride film on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a precursor to the substrate; (b) supplying a nitriding agent to the substrate; and (c) supplying an active species X, which is generated by plasma-exciting an inert gas, to the substrate, wherein a stress of the nitride film is controlled to be between a tensile stress and a compressive stress or is controlled to be the compressive stress by controlling an amount of exposure of the active species X to a surface of the substrate in (c).

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure includes alternatively disposed first nitride portions and second nitride portions wrapping portions of an oxide layer, a dielectric layer disposed between one of the first nitride portions and one of the second nitride portions, a top nitride surrounded by the one of the first nitride portions or the one of the second nitride portions, a filling material, and a cap layer disposed on the filling material; forming a plurality of trenches to expose the portions of the oxide layer wrapped by the first nitride portions and the second nitride portions; forming air gaps by removing the portions of the oxide layer; and conformally forming an encapsulating layer on inner sidewalls of the trenches to encapsulate the air gaps.

A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

A plasma processing apparatus for generating plasma from a processing gas using microwaves and performing plasma processing on a substrate is provided. The apparatus includes a processing chamber having a substrate support on which the substrate is placed; a plurality of microwave radiation units arranged at a central portion and an outer peripheral portion of a ceiling wall of the processing chamber and configured to radiate microwaves; and a controller configured to complete microwave radiation from the microwave radiation unit in the central portion upon completion of plasma processing of the substrate and then complete microwave radiation from the microwave radiation units in the outer peripheral portion.