A semiconductor structure includes a substrate, a gate structure, source/drain epitaxial structures, a contact structure, a first via structure, a metal line, a hard mask layer, a spacer layer, and a second via structure. The gate structure is formed over the substrate. The source/drain epitaxial structures are formed on opposite sides of the gate structure. The contact structure is formed over one of the source/drain epitaxial structures. The first via structure is formed over the contact structure. The metal line is electrically connected to the first via structure. The hard mask layer is formed over the metal line. The spacer layer is formed over a top surface of the hard mask layer and over a sidewall of metal line. The second via structure is formed over the metal line through the spacer layer.

Disclosed herein are devices and methods for forming split-gate transistors. In some embodiments, a method may include forming a high-k dielectric layer within a trench of a transistor, and forming a bottom electrode within a lower portion of the trench, wherein the bottom electrode is formed over the high-k dielectric layer. The method may further include forming a low-k dielectric layer over the bottom electrode, and forming a gate material over the low-k dielectric layer.

Methods, systems, and devices for a selective memory cell contact liner are described. A memory array may implement a protective liner within a memory cell structure including a cell contact for coupling memory storage material with an access device, a bit line associated with accessing the memory cell structure, and a bit line contact associated with activating the bit line. Forming the memory cell structure with the protective liner may include forming memory storage material, insulative material around the memory storage material, the bit line contact, the bit line, and the cavity. Then, a portion of the memory storage material may be replaced with a material associated with impeding deposition of the protective liner. The protective liner may be deposited within the cavity such that the bit line contact is covered by the protective liner but the memory storage material is not covered by the protective liner.

A method of manufacturing a semiconductor device includes providing a substrate including a molded structure and a mask layer on the molded structure, loading the substrate into an etching process chamber, performing an etching process on the loaded substrate and forming a plurality of recesses penetrating at least a portion of the molded structure, unloading the substrate from the etching process chamber, and performing a second semiconductor process on the unloaded substrate. The performing the etching process includes supplying an etching process gas including a first process gas and a second process gas including a fluorine-containing gas. In the forming the plurality of recesses, first by-products are formed. Second by-products are formed by a reaction of at least a portion of the first by-products and the second process gas.

Barrier-free interconnects and methods of fabrication thereof are disclosed herein. An exemplary interconnect structure has a conductive line disposed over a conductive via. The conductive line has a first conductive plug disposed in a first dielectric layer, and the first conductive plug includes an electrically conductive non-metal material, such as graphite. The conductive via includes a second conductive plug disposed in a second dielectric layer, and the second conductive plug includes a metal material, such as tungsten, ruthenium, molybdenum, or combinations thereof. The first conductive plug physically contacts the second conductive plug and the second dielectric layer. The second conductive plug physically contacts the second dielectric layer. Spacers (which are insulators) may be disposed between sidewalls of the first conductive plug and the first dielectric layer. The spacers may further be disposed between the first dielectric layer and the second dielectric layer.

An apparatus, a method and a system. The apparatus comprises a memory array including word lines defining a staircase structure, and a staircase etch stop layer including: a sandwich etch stop layer disposed on a top region the staircase and including a first etch stop layer and a third etch stop layer of a first material, and a second etch stop layer sandwiched between the first etch stop layer and the third etch stop layer and made of a second material having etch properties different from the first material; a precut etch stop layer disposed at a region of the staircase structure below the top region and including the second etch stop layer and the third etch stop layer and not the first etch stop layer; and contact structures extending through a dielectric layer and the staircase etch stop layer and landing on the word lines at the staircase structure.

A semiconductor structure includes a contact plug on a source/drain region of a transistor, and a via on the contact plug. The via includes a lower portion and an upper portion over the lower portion, the lower portion of the via tapers upward, and the upper portion of the via tapers downward. The semiconductor structure further includes a metal line on the via.

A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, a first dielectric layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The first dielectric layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.