Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

A semiconductor device structure includes a gate structure formed over a substrate. The semiconductor device structure also includes a source/drain structure formed beside the gate structure. The semiconductor device structure further includes a contact structure formed over the source/drain structure. The semiconductor device structure also includes a first cap layer formed over the contact structure. The semiconductor device structure further includes a dielectric structure extending from a top surface of the first cap layer into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.

A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.

A method includes obtaining a base structure including a stack of dielectric layers disposed on a substrate. The stack of dielectric layers includes a first photosensitive dielectric layer including a first photosensitive dielectric material sensitive to a first radiation dose, a second photosensitive dielectric layer including a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose, and a barrier layer disposed between the first photosensitive dielectric layer and the second photosensitive dielectric layer. The method further includes forming a dual damascene structure from the base structure using a dual damascene process.

A device comprises a non-insulator structure, a dielectric layer, a metal via, a metal line, and a dielectric structure. The dielectric layer is over the non-insulator structure. The metal via is in a lower portion of the dielectric layer. The metal line is in an upper portion of the dielectric layer. The dielectric structure is embedded in a recessed region in the lower portion of the dielectric layer. The dielectric structure has a tapered top portion interfacing the metal via.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a conductive structure including a conductive concave layer positioned on the substrate and including a top surface having a V-shaped cross-sectional profile; and a conductive filling layer positioned on the conductive concave layer; and a top conductive layer positioned on the conductive structure. The conductive filling layer includes germanium or silicon germanium.

An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of dielectric materials interleaved with levels of conductive materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending in a direction from the first conductive level to the second conductive level, the second conductive level including a side wall; a conductive contact extending in the direction from the first conductive level to the second conductive level and contacting the second conductive level; a first dielectric material between the first conductive level and the conductive contact, the first dielectric material having a first dielectric constant; and a second dielectric material between the first dielectric material and the conductive contact, the second dielectric material having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant.

A microelectronic device includes a stack with vertically repeated tiers respectively including insulative and conductive structure(s). Slits divide the stack into blocks. Within a block, a series of stadiums is formed with stadiums horizontally spaced by crests. The stadiums are individually defined in unique groups of the tiers and include staircase(s). A first stadium of the series is defined in a first tier group elevationally above a second tier group in which a second stadium is defined. Step contacts extend to or into steps of the staircase(s). Through-stack vias extend a height of the stack and are in electrical communication with the step contacts. Some through-stack vias are within the first stadium area and are in electrical communication with the first stadium's step contacts. Other through-stack vias are within the crests and are in electrical communication with the second stadium's step contacts. Related methods and systems are also disclosed.