A semiconductor chip includes: a photonic integrated circuit (PIC) comprising an active component electrically connected to a first landing pad at a surface of the PIC, wherein the first landing pad is configured to receive a copper pillar, which, when installed, provides at least a portion of a first electrical interconnect between the active photonic component and a second integrated circuit to be stacked on the surface of the PIC, and wherein, when viewed from above the PIC towards the PIC, a center of the active photonic component on the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

A semiconductor package, as a semiconductor package mounted on a circuit board, includes including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.

A semiconductor package includes a redistribution structure including a wiring structure and an insulating structure covering the wiring structure, the redistribution structure having a first surface and a second surface, which are opposite to each other, the insulating structure including a polymer, a semiconductor chip on the first surface, the semiconductor chip being connected to at least one first wiring pattern in the wiring structure, a passivation insulating film covering the second surface, the passivation insulating film including an inner surface contacting the insulating structure and a hole sidewall defining a hole, the passivation insulating film including an inorganic insulating material, a conductive pad passing through the passivation insulating film via the hole and contacting the second wiring pattern, the conductive pad having a pad sidewall contacting the hole sidewall, and an external connection terminal on the conductive pad.

A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.

A semiconductor package structure and a method for preparing the same are provided. The semiconductor package structure includes: a substrate; a first semiconductor chip located on the substrate, the first semiconductor chip having a first surface that is bare and the first surface having a silicon-containing surface; second semiconductor chip structures located on the first surface of the first semiconductor chip, the second semiconductor chip structures having second surfaces opposite to the first surface; a first package compound structure having a joint surface, the joint surface covering at least the first surface of the first semiconductor chip and the second surfaces of the second semiconductor chip structures. The joint surface has a silicon-containing surface.

A method of manufacturing a display device includes forming a thin film transistor layer in an active area of a substrate, forming a metal layer on an edge area of the substrate, transferring first coating patterns to the edge area, the first coating patterns covering a portion of the metal layer corresponding to shapes of side surface lines, etching the metal layer to form the side surface lines, an upper surface of each of the side surface lines being covered by the first coating patterns, transferring a second coating pattern to the edge area, the second coating pattern covering a side surface of each of the side surface lines and the first coating patterns, and transferring light emitting elements to the thin film transistor layer. The second coating pattern includes openings corresponding to the first coating patterns in a plan view.

A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.