A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.

The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

A heteroepitaxial semiconductor device includes a bulk semiconductor substrate, a seed layer including a first semiconductor material, the seed layer being arranged at a first side of the bulk semiconductor substrate and including a first side facing the bulk semiconductor substrate, an opposing second side and lateral sides connecting the first and second sides, a separation layer arranged between the bulk semiconductor substrate and the seed layer, a heteroepitaxial structure grown on the second side of the seed layer and including a second semiconductor material, different from the first semiconductor material, and a dielectric material layer arranged on the seed layer and at least partially encapsulating the heteroepitaxial structure, wherein the dielectric material layer also covers the lateral sides of the seed layer.

A method for growing a III-V material may include forming at least one layer on a stack including a crystalline layer made of III-V material, a first masking layer surmounting the germination layer, the first masking layer having at least one first opening; depositing a second masking layer covering an upper face of the sacrificial layer; forming at least one second opening in the second masking layer; removing the sacrificial layer selectively at the first masking layer and at the second masking layer; epitaxially growing a material made of the III-V material from the germination layer; forming al least one third opening in the second masking layer; and epitaxially growing at least one material made of the III-V material from the first epitaxial layer.

A preparation method of an aluminum nitride (AlN) composite structure based on a two-dimensional (2D) crystal transition layer is provided. The preparation method includes: transferring the 2D crystal transition layer on a first periodic groove of an epitaxial substrate; forming a second periodic groove staggered with the first periodic groove on the 2D crystal transition layer; depositing a supporting protective layer; depositing a functional layer of a required AlN-based material; and removing the 2D crystal transition layer through thermal oxidation to obtain a semi-suspended AlN composite structure. The preparation method has low difficulty and is suitable for large-scale industrial production. Design windows of the periodic grooves and the AlN functional layer are large and can meet the material requirements of deep ultraviolet light-emitting diodes (DUV-LEDs) and radio frequency (RF) electronic devices for different purposes, resulting in a wide application range.

A method of forming regrown fiducials includes providing a III-V compound substrate having a device region and an alignment mark region. The III-V compound substrate is characterized by a processing surface. The method also includes forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface and etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches. The method also includes epitaxially regrowing a semiconductor layer in the trenches to form the regrown fiducials extending to a predetermined height over the processing surface in the alignment mark region.

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.