Embodiments of the present invention generally relate to methods of epitaxially growing boron-containing structures. In an embodiment, a method of depositing a structure comprising boron and a Group IV element on a substrate is provided. The method includes heating the substrate at a temperature of about 300 C. or more within a chamber, the substrate having a dielectric material and a single crystal formed thereon. The method further includes flowing a first process gas and a second process gas into the chamber, wherein: the first process gas comprises at least one boron-containing gas comprising a haloborane; and the second process gas comprises at least one Group IV element-containing gas. The method further includes exposing the substrate to the first and second process gases to epitaxially and selectively deposit the structure comprising boron and the Group IV element on the single crystal.

Methods for forming structures that include forming a heteroepitaxial layer on a substrate are disclosed. The presently disclosed methods comprise epitaxially forming a buffer layer on the substrate. The substrate has a substrate composition. The buffer layer has a buffer layer composition. The buffer layer composition is substantially identical to the substrate composition. The presently disclosed methods further comprise epitaxially forming a heteroepitaxial layer on the buffer layer. The heteroepitaxial layer has a heteroepitaxial layer composition which is different from the substrate composition.

The present disclosure generally relates to semiconductor processing for forming an emitter layer in a bipolar junction transistor (BJT). In an example, a BJT includes a collector, a base on the collector, and an emitter layer on the base. The emitter layer includes a first emitter sub-layer and a second emitter sub-layer over the first emitter sub-layer. The first emitter sub-layer includes boron and carbon. A concentration of carbon is uniform throughout the first emitter sub-layer. The second emitter sub-layer includes boron. A concentration of boron in the second emitter sub-layer is greater than a concentration of boron in the first emitter sub-layer.

Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCl, Cl2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source/drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

A super junction device with an increased voltage rating may be formed by creating a P liner on the sidewalls of a trench etched into N material, then filling the trench with additional N-type material. This thin P liner may be doped at a significantly higher concentration than the surrounding N material to maintain a charge balance. However, these relatively thin dimensions and the high doping concentration differential may cause P dopants to diffuse into the N material during subsequent high-temperature manufacturing processes. Diffusion barriers on either side of the P liner prevent diffusion of the dopants into the surrounding N material. The diffusion barriers create an abrupt interface between the N and P materials that prevents diffusion and improves the performance of the super junction devices.

A processing chamber with a top, a bottom, and a sidewall coupled together to define an enclosure, a substrate support having a substrate supporting surface, an energy source coupled to the top or the bottom, and a gas injector liner disposed at the sidewall. The gas injector liner comprises a first plurality of gas outlets disposed at a first height, wherein one or more of the first plurality of gas outlets are oriented upwardly or downwardly, a second plurality of gas outlets disposed at a second height shorter than the first height, wherein one or more of the second plurality of gas outlets are oriented upwardly or downwardly, and a third plurality of gas outlets disposed at a third height shorter than the second height, wherein one or more of the third plurality of gas outlets are oriented upwardly or downwardly with respect to the substrate supporting surface.

A method of forming silicon within a gap on a surface of a substrate. The method includes use of two or more pyrometers to measure temperatures at two or more positions on a substrate and/or a substrate support and a plurality of heaters that can be divided into zones of heaters, wherein the heaters or zones of heaters can be independently controlled based on the measured temperatures and desired temperature profiles.

A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

A halotrisilane preparation method may include providing a reactant that contains halotrisilane including M halogen atoms (where, M may be a natural number from 2 to 8), reducing the halotrisilane in the reactant by using a mixed reducing agent that includes a first reducing agent represented by Formula 1-1 and a second reducing agent represented by Formula 2-1, and obtaining a product that contains the reduced halotrisilane that includes N halogen atoms, where N may be a natural number from 1 to 7 and where N<M.

[00001]$\begin{array}{cc}{\left(R_A\right)}_a-\mathrm{Al}-H_b& \left[\mathrm{Formula}1-1\right]\end{array}$

In Formula 1-1 above, R.sub.A may represent an alkyl group, a and b each may be either 1 or 2, and a+b=3.

[00002]$\begin{array}{cc}{\left(R_S\right)}_p-\mathrm{Sn}-H_q& \left[\mathrm{Formula}2-1\right]\end{array}$

In Formula 2-1 above, R.sub.S may represent an alkyl group or an aryl group, p and q each independently may be a natural number from 1 to 3, and p+q=4.