Embodiments of the present disclosure generally relate to epitaxial processes and materials, and more specifically, epitaxial processes for preparing materials, layers, stacks, and devices. In one or more embodiments, a device includes a multi-layer structure disposed on a substrate. The multi-layer structure includes a plurality of doped silicon-germanium (SiGe) layers. The doped SiGe layers respectively include a dopant having a concentration in a range from about 0.01 atomic percent (at%) to about 5 at%. The multi-layer structure includes a plurality of silicon layers disposed in an alternating arrangement with the doped SiGe layers such that a respective silicon layer is disposed between a respective first doped SiGe layer and a respective second doped SiGe layer.

A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate.

A system for controlling flatness of an epitaxial semiconductor wafer includes a polishing assembly, a measuring device, and a computer system in communication with the polishing assembly and the measuring device. The computer system stores and executes instructions that cause the computer system to measure one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus, polish a semiconductor wafer using a polishing assembly and measure the polished semiconductor wafer to determine a surface profile of the polished wafer, generate a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus, determine a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjust, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.

Methods and systems for epitaxial deposition using X-ray fluorescence (XRF) measurements and process control techniques are provided. The method involves performing an epitaxial deposition process to deposit alternating layers of silicon (Si) and silicon germanium (SiGe) on a substrate. XRF measurements determine the thickness and composition of these layers, allowing for precise control over layer thickness and composition. The process helps maintain the targeted strain and prevents defects, improving device performance. The XRF measurements can be performed in-situ or in a transfer chamber, enabling real-time adjustments to the deposition parameters. The method is applicable to various semiconductor devices, including 3D DRAM and gate-all-around (GAA) transistor devices.

Transistors with raised source/drain structures and methods of making the transistors are described. A method for making such transistors includes forming a first gate and a second gate on a substrate, forming a p-doped region adjacent the first gate, and forming an n-doped region adjacent the second gate. The method further includes forming a silicon germanium (SiGe) region in a portion of the p-doped region. Subsequently, the method simultaneously forms raised source-drain structures over the SiGe region and on the n-doped region.

A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein each fin of the plurality of fins includes silicon germanium. A layer of silicon germanium oxide is deposited on the plurality of fins, and a first thermal annealing process is performed to convert outer regions of the plurality of fins into a plurality of silicon portions. Each silicon portion of the plurality of silicon portions is formed on a silicon germanium core portion. The method further includes forming a plurality of source/drain regions on the substrate, and depositing a layer of germanium oxide on the plurality of source/drain regions. A second thermal annealing process is performed to convert outer regions of the plurality of source/drain regions into a plurality of germanium condensed portions.

A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.

An epitaxial silicon carbide substrate comprises a first epitaxial silicon carbide layer and at least a second silicon carbide epitaxial layer. A plurality of devices are formed in or overlying the second silicon carbide epitaxial layer. The epitaxial silicon carbide substrate is formed overlying a reuseable silicon carbide substrate. An exfoliation layer is at or underlies a surface of the reuseable silicon carbide substrate. The exfoliation layer comprises silicon carbide and carbon. In one embodiment a plurality of trenches is formed in the surface of the reuseable silicon carbide substrate. The layer of carbon is formed in or below the plurality of trenches. An exfoliation process comprises thermal or mechanical processes to separate the reuseable silicon carbide substrate from the epitaxial silicon carbide substrate. The surface of the reuseable silicon carbide substrate is prepared so the reuseable silicon carbide substrate can be reused.

A semiconductor structure and the manufacturing method thereof are provided. The semiconductor structure comprises a silicon substrate, a nitride buffer composite layer, an active layer and a silicon barrier composite layer. The nitride buffer composite layer is disposed above the silicon substrate, the active layer is disposed above the nitride buffer composite layer, and the silicon barrier composite layer is interposed within the nitride buffer composite layer to substantially block the diffusion of silicon impurities from the silicon substrate to reduce leakage current.