Disclosed is a method of processing a substrate, the method including: a heating operation of irradiating a substrate with a laser generated from a laser source and heating the substrate, in which the heating operation includes: a laser splitting operation of splitting the laser into a plurality of beamlets using an optical modulation unit; and a laser irradiating operation of irradiating the substrate with the plurality of beamlets, and the plurality of beamlets is emitted so as not to overlap or be connected to one another.

Disclosed is a substrate processing method including: supplying a processing liquid onto a rotating substrate; and irradiating, by the laser irradiation assembly, the rotating substrate, on which a liquid film of the processing liquid is formed, with a laser to heat the substrate, in which the substrate is divided into one or more unit irradiation areas, the laser irradiation assembly designates any one of the one or more unit irradiation areas and irradiates the designated unit irradiation area with the laser, and synchronizes an oscillation frequency of the laser with a rotation speed of the substrate so that an irradiation position of the laser is the designated unit irradiation area.

The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

A method includes forming first sacrificial layers and first channel layers alternately stacked over a substrate; forming second channel layers and second sacrificial layers alternately stacked over the first sacrificial layers and the first channel layers, in which the second channel layers are made of a first semiconductive oxide; performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers; forming a gate structure in contact with the first channel layers and the second channel layers; forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers; and forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.

A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Embodiments herein relate to methods, apparatus, and systems for selectively etching a substrate. The substrate typically includes one or more layers of silicon and one or more layers of silicon germanium. The method may involve receiving the substrate in a process chamber; exposing the substrate to F.sub.2; and exposing the substrate to an additive, where exposing the substrate to F.sub.2 and to the additive results in selectively etching the silicon germanium compared to the silicon, and where the substrate is not exposed to plasma while exposed to F.sub.2. Use of the additive produces a more uniform etch rate for the material being etched than would otherwise be achieved in the absence of the additive.

The present disclosure provides a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.

A method for manufacturing raised strip-shaped active areas is disclosed, including: step 1: performing etching on a semiconductor substrate to form patterning raised strip-shaped structures and shallow trenches; step 2: forming a second dielectric layer which fills the shallow trenches and extends to a surface of the first hard mask layer on top surfaces of the raised strip-shaped structures; step 3: performing the first CMP on second dielectric layer, the first CMP stops at a surface of a first hard mask layer; step 4: performing planarization adjustment on a top surface of the second dielectric layer through second wet etching to reduce a height difference of the top surface of the second dielectric layer in different areas; step 5: removing the first hard mask layer; and step 6: performing third dry etching to reduce the top surface of the second dielectric layer to below the top surface of each raised strip-shaped structure.

A method for forming an SOI substrate includes following operations. A first semiconductor layer, a second semiconductor layer and a third semiconductor layer are formed over a first substrate. A plurality of trenches and a plurality of recesses are formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer. The plurality of trenches extend along a first direction, and the plurality of recesses extend along a second direction different from the first direction. The plurality of trenches and the plurality of recesses are sealed to form a plurality of voids. A device layer is formed over the first substrate. The devices layer is bonded to an insulator layer over a second substrate. The third semiconductor layer, the device layer the insulator layer and the second substrate are separated from the first semiconductor layer and the first substrate. The device layer is exposed.

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Fe.sup.+3 ions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described.