A substrate processing apparatus according to the present invention includes a step (immersing step) of immersing a substrate array that is a horizontal arrangement of vertically oriented substrates in sulfuric acid, a step (elevating step) of elevating an entirety of the substrate array from the sulfuric acid, and a step (mist supplying step) of supplying mist of hydrogen peroxide solution to the substrate array having been elevated. With this configuration, only the liquid sulfuric acid film attached to the surface of the substrate is turned into SPM. In this manner, much less hydrogen peroxide solution is consumed, as compared with that in a conventional method.

A method for manufacturing a semiconductor structure includes forming a plurality of semiconductor stack portions spaced apart from each other by a plurality of recesses, each of which includes two sacrificial layer portions and a channel layer portion disposed therebetween, in which the channel layer portion has a plurality of crystal planes and is formed with a first straight lateral surface which is aligned with one of the crystal planes that has a lowest etching rate for an etchant to be used for laterally etching the channel layer portion among those of the crystal planes of the channel layer portion which are able to expose to the recesses; and laterally etching the channel layer portion using the etchant to permit the channel layer portion to be formed with a second straight lateral surface.

A method of manufacturing single-photon detector includes forming a first electrode on a front side of a substrate, removing the substrate and preforming ion implantation on a backside of an epitaxial layer to form a contact region for a second electrode, which extends from the surface of the epitaxial layer to a first predetermined depth within the epitaxial layer. The second electrode is be electrically connected to the contact region for the second electrode. Since the substrate is removed, the epitaxial layer, which is provided as a semiconductor layer, has a uniform thickness. The contact region for the second electrode has a uniform thickness, and its dopant concentration is easy to control and adjust. Thus, the second electrode can be formed so as to have uniform contact resistance across its different regions.

A wafer bonding method includes: disposing a device wafer on a carrier wafer to form an interface between the device wafer and the carrier wafer and a back surface of the device wafer opposite to the interface; forming a step structure at an upper corner of the back surface of the device wafer, so that the back surface of the device wafer has a profile of an external portion being higher than an inner portion; and performing a thinning process with an etching solution to the inner portion of the back surface of the device wafer.

According to the disclosure, provided is an etching agent for etching a semiconductor substrate having a surface partially covered with a noble metal, the etching agent including: an oxidizing agent; hydrogen fluoride; and ammonium fluoride. 0.5n/m5.0 is satisfied, where m is a molar concentration [mol/L] of the hydrogen fluoride, and n is a molar concentration [mol/L] of the ammonium fluoride.

A semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. The semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. The subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. The semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. In the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.

A method includes depositing a silicon layer over a semiconductor region, forming dielectric isolation regions extending into the silicon layer and the semiconductor region, and recessing the dielectric isolation regions. A first portion of the silicon layer and a second portion of the semiconductor region are between the dielectric isolation regions, and protrude higher than top surfaces of the dielectric isolation regions to form a semiconductor fin. The semiconductor fin is thinned, and after the first semiconductor fin is thinned, the first portion of the silicon layer remains. A gate stack is formed on the semiconductor fin.

An etching method includes a first etching step, a processing step, and a second etching step. The first etching step is performed to etch a substrate on which a silicon oxide film and a silicon nitride film are formed with an etching liquid. The processing step is performed to process a pattern in the silicon oxide film on the substrate with a pattern shape processing liquid after the first etching step. The second etching step is performed to etch the substrate with the etching liquid after the processing step.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

A composition for semiconductor processing according to the disclosure contains (A) a compound represented by the following general formula (1), (B) a compound represented by the following general formula (2), (C) a compound having at least one functional group selected from the group consisting of an amino group and a salt thereof (excluding a compound having a carboxyl group and a nitrogen-containing heterocyclic compound) and (D) a liquid medium, and, when the content of the (A) component is indicated by M.sub.A [mass %] and the content of the (B) component is indicated by M.sub.B [mass %], M.sub.A/M.sub.B is 1.010.sup.2 to 1.010.sup.6.
RO(CH.sub.2).sub.2O(CH.sub.2).sub.2OH(1)
ROH(2) (In the formula (1) and the formula (2), R's represent the same hydrocarbon group.)