H10P72/74

Package structure and method of fabricating the same

A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

Wafer carrier and method

A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

MICROFLUIDIC TRANSFER SUBSTRATE AND METHOD FOR TRANSFERRING LIGHT-EMITTING ELEMENTS
20260013285 · 2026-01-08 · ·

A microfluidic transfer substrate includes a transfer area and a liquid droplet input area. The transfer area includes a plurality of pixel groups. Each pixel group includes at least three first pixel units. One first pixel unit of each pixel group serves as a first microfluidic pixel and a surface of the first microfluidic pixel defines an assembly groove. The plurality of pixel groups include first color pixel groups, second color pixel groups, and third color pixel groups. The liquid droplet input area includes a first color liquid droplet input area, a second color liquid droplet input area, and a third color liquid droplet input area, which are configured to generate and transport liquid droplets containing a first color light-emitting element, a second color light-emitting element, and a third color light-emitting element to the transfer area, respectively. A method for transferring the light-emitting elements is further provided.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE

A semiconductor device includes a semiconductor element, a sealing member, and a rewiring layer. The rewiring layer includes an insulating layer covering a front surface of the semiconductor element and a part of the sealing member, an electrode connected to the semiconductor element, and an externally-exposed layer being conductive and covering a portion of the electrode exposed from the insulating layer.

Method for Collective Dishing of Singulated Dies

Methods for substrate processing include attaching a plurality of dies to a first carrier, wherein each die has a first side and a second side opposite the first side, wherein the first side is attached to the first carrier and wherein the plurality of dies are spaced horizontally from one another on the first carrier; filling spaces between the plurality of dies and covering the second sides of the plurality of dies with a dielectric or metal; grinding or polishing the dielectric or metal covering the second sides and grinding or polishing the second sides until the second sides are exposed and the plurality of dies have a substantially uniform thickness; and after grinding or polishing, dishing die faces of the plurality of dies to a desired dishing profile.

TEMPORARY FIXATION SUBSTRATE AND METHOD OF MANUFACTURING TEMPORARY FIXATION SUBSTRATE
20260011597 · 2026-01-08 ·

A temporary fixation substrate, peeled from a predetermined object to be fixed after once the predetermined object to be fixed is temporarily fixed to one main surface thereof, includes: a thin region being an annular region having a predetermined width from a lateral end; and a first thickness-reduced portion having been recessed from the one main surface on a side of the one main surface in the thin region, wherein a thickness in the thin region is smaller than a thickness in a region other than the thin region, and a difference between a thickness at the lateral end and the thickness in the region other than the thin region is 1 m to 5 m.

ADHESIVE SHEET FOR PROVISIONAL FIXATION OF ELECTRONIC COMPONENT

Provided is an adhesive/pressure-sensitive adhesive sheet for temporarily fixing an electronic part having a photothermal conversion function, the adhesive/pressure-sensitive adhesive sheet for temporarily fixing an electronic part having excellent heat resistance. The adhesive/pressure-sensitive adhesive sheet for temporarily fixing an electronic part according to an embodiment of the present invention includes a photothermal conversion layer. The adhesive/pressure-sensitive adhesive sheet for temporarily fixing an electronic part has a transmittance for light having a wavelength of 1,032 nm of 60% or less. The adhesive/pressure-sensitive adhesive sheet for temporarily fixing an electronic part has a transmittance for light having a wavelength of 355 nm of 60% or less. The photothermal conversion layer contains carbon black. The photothermal conversion layer has a 5% weight loss temperature after UV irradiation of 300 C. or more.

Semiconductor device and method of forming vertical interconnect structure for pop module

A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.

Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer

A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

Panel-Level Chip Packaging Structure and Method Based on Steel Plate Platform
20260018549 · 2026-01-15 ·

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a panel-level chip packaging structure and method based on a steel plate platform. The packaging structure includes: a steel plate; a gold-nickel layer plated on the steel plate, where the gold-nickel layer is provided with upwardly protruding pins corresponding to a chip; the chip flipped to the corresponding pins; and a molded body coating the corresponding chip and the gold-nickel layer. According to the packaging structure and method of the present disclosure, an overall thickness of a chip-packaged product can be reduced. A wire bonding process and an electroplating process are further omitted, so that the overall thickness of chip packaging can be further reduced. An ultra-thin packaging structure can be implemented, the chip packaging efficiency can further be improved, and a complete-process chip packaging cycle can be shortened.