Patent classifications
H10P72/74
METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT
A method of manufacturing a semiconductor element includes preparing integrated circuit chips, obtaining warpage information of each of the integrated circuit chips, deforming at least a portion of a chip stress control pattern of each of the integrated circuit chips according to the warpage information of each of the integrated circuit chips, laminating the integrated circuit chips on a carrier substrate with adhesive layers interposed therebetween, curing the adhesive layers, and removing chip scribe lane areas from the integrated circuit chips.
MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERS
An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.
MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER
A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.
ELEMENT TRANSFER DEVICE AND ELEMENT TRANSFER METHOD
An element transfer device includes a support substrate holding part that holds a support substrate on which an element is supported via an adhesive layer, a laser light irradiation unit that is disposed on a side opposite to a surface on which the element is supported by the support substrate and irradiates laser light toward the support substrate, and a control unit that controls an irradiation position of the laser light irradiated from the laser light irradiation unit. An area of a spot area of the laser light is smaller than an area of a surface of the element supported by the support substrate. The control unit controls the irradiation position of the laser light such that the laser light is irradiated from one end side of the element to the other end side while moving relative to the support substrate.
Bonding and indexing method
A bonding and indexing method is provided, having a first index head to move a substrate in an indexing direction from a first position to a second position; a second index head to move the substrate in an indexing direction from the second position to a third position; and the first and/or second index head has a bonding element to effect a bonding process between the substrate and an element disposed against the substrate so that bonding and movement in the indexing direction is implemented simultaneously by the first index head and/or bonding and movement in the indexing direction is implemented simultaneously by the second index head.
Method of preparing a device coupon for micro-transfer printing, device wafer including said device coupon, and optoelectronic device manufactured from said device wafer
A method of preparing a device coupon for a micro-transfer printing process from a multi-layered stack located on a device wafer substrate. The multi-layered stack comprises a plurality of semiconductor layers. The method comprises steps of: (a) etching the multi-layered stack to form a multi-layered device coupon, including an optical component; and (b) etching a semiconductor layer of the multi-layered device coupon to form one or more tethers, said tethers securing the multi-layered device coupon to one or more supports.
Methods for fusion bonding semiconductor devices to temporary carrier wafers with hydrophobic regions for reduced bond strength, and semiconductor device assemblies formed by the same
Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.
DONOR
A donor includes: a substrate; a resin layer disposed on the substrate and including a base portion and a plurality of protrusions; and a glass layer disposed between the plurality of protrusions on the resin layer.
IMPLANTABLE EMBEDDED SYSTEMS AND RELATED MANUFACTURING METHODS
Embodiments described herein include a method for manufacturing a neural implant including patterning a circuit-bearing substrate to produce a first intermediate structure having a plurality of electrode contacts disposed on a first side thereof. The method can include applying an encapsulation layer to the first side of the first intermediate structure to produce a second intermediate structure and coupling a first surface of the second intermediate structure to a carrier, the first surface of the second intermediate structure including the encapsulating layer. The method can include thinning the second intermediate structure to produce a third intermediate structure and forming a plurality of recesses in a portion of the third intermediate structure to produce a fourth intermediate structure. The method can include releasing the carrier from the fourth intermediate structure to produce the neural implant.
SEMICONDUCTOR DIE RELEASING WITHIN CARRIER WAFER
A semiconductor die assembly is introduced in this disclosure. The semiconductor die assembly includes one or more semiconductor dies, a dielectric layer disposed under a bottom surface of the one or more semiconductor dies, and metal fragments or a metal layer disposed under the dielectric layer, wherein metal-OH bonds or metal-OSiOH bonds are disposed on a bottom surface of the dielectric layer. Alternatively, the semiconductor die assembly includes one or more semiconductor dies, a metal layer disposed under a bottom surface of the one or more semiconductor dies, and a metal oxidation layer disposed under the dielectric layer, wherein the metal oxidation layer comprises metal-OH bonds or metal-OSiOH bonds.