A power semiconductor device includes a semiconductor structure comprising an active region, an encapsulation material on the semiconductor structure, and a plurality of adhesion features in or on the semiconductor structure along an interface with the encapsulation material. The interface is laterally between the active region and at least one edge of the semiconductor structure. Related devices and fabrication methods are also discussed.

A wiring substrate includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third conductive layer, a third insulating layer, and a fourth conductive layer. Given that an occupancy ratio of a first conductive pattern in the first conductive layer is a first occupancy ratio, an occupancy ratio of a second conductive pattern in the second conductive layer is a second occupancy ratio, an occupancy ratio of a third conductive pattern in the third conductive layer is a third occupancy ratio, and an occupancy ratio of a fourth conductive pattern in the fourth conductive layer is a fourth occupancy ratio, each of the first occupancy ratio and the third occupancy ratio is greater than each of the second occupancy ratio and the fourth occupancy ratio.

A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface. The first redistribution structure includes a first pad and a second pad, the first pad is adjacent to the first surface, and the second pad is adjacent to and exposed from the second surface. The chip package structure includes a chip package bonded to the first pad through a first bump, wherein a first width of the first pad decreases in a first direction away from the chip package, and a second width of the second pad decreases in the first direction. The chip package structure includes a second bump over the second pad.

A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

A semiconductor package includes a first component, a second component, and a stiffener rib. The first component is disposed on a substrate. The second component is disposed aside the first component and on the substrate. The stiffener rib is disposed between the first component and the second component. The lid is attached to the stiffener rib, the first component and the second component. The lid includes a recess portion on the stiffener rib. A first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib. A first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

A package includes a substrate. The package further includes a first die on the substrate. The package further includes a second die on the substrate. The package further includes a first stress relief structure on the substrate, wherein a distance between the first stress relief structure to the first die is a first distance. The package further includes a second stress relief structure on the substrate, wherein a distance between the second stress relief structure to the first distance, and the second stress relief structure is separated from the first stress relief structure.

Semiconductor systems having anti-warpage frames (and associated systems, devices, and methods) are described herein. In one embodiment, a semiconductor system includes (a) a printed circuit board (PCB) having a first side and a second side opposite the first side, and (b) at least one memory device attached to the PCB at the first side of the PCB. The semiconductor system further includes a frame structure attached to the PCB at the first side of the PCB and proximate the at least one memory device. The frame structure can be configured to resist warpage of the PCB, for example, when the semiconductor system is heated to attach the at least one memory device to the PCB.

A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

An electronic package technology is disclosed. A first active die can be mountable to and electrically coupleable to a package substrate. A second active die can be disposed on a top side of the first active die, the second active die being electrically coupleable to one or both of the first active die and the package substrate. At least one open space can be available on the top side of the first active die. At least a portion of a stiffener can substantially fill the at least one open space available on the top side of the first active die.