A microelectronic assembly comprises a first microelectronic component; a second microelectronic component under an area of the first microelectronic component and coupled to the first component through first interconnect structures within a central region of the area, and second interconnect structures within a peripheral region of the area, adjacent to the central region. A heterogenous dielectric surface on the first or second component or both and within a gap between the first and second components has a first surface composition within the central region and at least a second surface composition within the peripheral region.

In one example, an electronic device, comprises a substrate comprising a dielectric structure and a conductive structure, an electronic component over a top side of the substrate, wherein the electronic component is coupled with the conductive structure; an encapsulant over the top side of the substrate and contacting a lateral side of the electronic component, wherein the encapsulant comprises a first trench on a top side of the encapsulant adjacent to the electronic component, a lid over the top side of the encapsulant and covering the electronic component; and an interface material between the top side of the encapsulant and the lid, and in the first trench. Other examples and related methods are also disclosed herein.

A memory module, includes a module substrate and at least one semiconductor package on the module substrate that includes a package substrate having a lower surface and an upper surface. First and second groups of lower pads are on the lower surface, and upper pads are on the upper surface and are electrically connected to the lower pads of the first group. A chip structure is on the upper surface of the package substrate and is electrically connected to the upper pads. First connection bumps connect the lower pads of the first group to the module substrate, and second connection bumps connect the lower pads of the second group to the module substrate. The first connection bumps have a first maximum width at a first distance from the package substrate, and the second connection bumps have a second maximum width at a second, shorter distance from the package substrate.

An embedded packaging structure includes an optical communication device embedded in a substrate, and a blocking wall surrounding the working face opening. The optical communication device may include a working face for emitting light or receiving light. The working face may be revealed by a working face opening from a first surface of the substrate. The blocking wall may extend beyond the first surface in a direction away from the first surface.

A semiconductor package according to some example embodiments may include a chip base including a main chip region and an edge region around the main chip region, a device layer on the chip base, a wiring layer on the device layer, an upper insulating stack on the wiring layer, and a trench on the edge region, the trench recessed from the upper insulating stack to the device layer, and an inner surface of the trench exposed to an outside of the semiconductor chip.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.

A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

A method for making an electronic package is provided. The method includes providing a substrate strip comprising substrate assemblies, each substrate assembly comprises a first substrate and a second substrate connected to the first substrate via a flexible link, the first substrate comprises a first mounting surface, the second substrate comprises a second mounting surface that is not at a same side of the substrate assembly as the first mounting surface; disposing the substrate strip on a first carrier; attaching a first electronic component onto the first mounting surface; disposing the substrate strip on a second carrier with a plurality of cavities, the first electronic component is received within one of the plurality of cavities; attaching a second electronic component onto the second mounting surface; singulating the substrate assemblies from each other; and bending the flexible link to form an angle between the first substrate and the second substrate.

Embodiments herein relate to systems, apparatuses, or processes for packages that include a high-speed transmission line that is routed from a compute die on a substrate under a silicon die that is next to the compute die on the substrate. The silicon die includes a ground plane above the high-speed transmission line. The high-speed transmission line is at least partially between the ground plane of the silicon die and another ground plane within the substrate. Other embodiments may be described and/or claimed.