A memory system comprises a monolithic integration of a NAND die, a MRAM die and one or more control dies positioned in a same semiconductor package for high speed and high density non-volatile data storage. The MRAM die can be operated as a cache for the NAND die or to provide long term data storage for data not cached for the NAND die. In one embodiment, the NAND die comprises a plurality of NAND strings. The MRAM die comprises a MRAM structure. The one or more control dies comprise one or more control circuits for operating the NAND die and the MRAM die.

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a semiconductor substrate and a second bonding structure over the semiconductor substrate. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. Sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate. The first connectors are in physical contact with the second connectors. The first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer. The encapsulant laterally encapsulates the second die. The TIVs are aside the second die.

According to one embodiment, a semiconductor device includes a wiring board, a first semiconductor module that includes one or more first semiconductor chips staked together, a wire that connects one of the one or more first semiconductor chips to the wiring board, and a second semiconductor module that is arranged adjacent to the first semiconductor module and includes second semiconductor chips stacked together. At least part of the wire is in contact with an adhesive layer between an N-th second semiconductor chip and an (N+1)th second semiconductor chip from a lowermost layer among the second semiconductor chips.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

Methods and apparatus to reduce thickness of on-package memory architectures are disclosed. An on-package memory architecture includes a memory die; a bonding pad including a first surface and a second surface opposite the first surface; a wire bond electrically coupling the memory die to the first surface of the bonding pad; and a metal stub protruding from the second surface of the bonding pad. The metal stub is to electrically couple with a contact pad on a package substrate of an integrated circuit (IC) package.

Methods, systems, and devices for thermal mitigation for multi-chip memory systems are described. For example, the described techniques may support one or more heat transfer components to contact one or more controller dies of a multi-chip package (MCP) that also includes one or more memory array dies. For example, a layer of a mold compound material may be removed to expose a top surface of a controller die, and a heat transfer component may be attached in contact with the top surface of the controller die. Additionally, or alternatively, a heat transfer component may be attached to a top surface of a controller die prior to forming a mold compound material. The mold compound material may be formed over the controller die and heat transfer component, and a portion of the mold compound material may be removed to expose a top surface of the heat transfer component.

A stacked system-on-chip (SoC) is described. The stacked SoC comprises a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also comprises a compute logic die. The compute logic die comprises a static random-access memory (SRAM) comprising a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die comprises a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

A semiconductor device includes: an interconnect substrate including a plurality of interconnect layers; a first semiconductor chip disposed over the interconnect substrate; a second semiconductor chip disposed over the first semiconductor chip in a shifted manner and including a plurality of metal bumps on a surface of the second semiconductor chip facing the interconnect substrate; and a plurality of columnar electrodes connecting the interconnect structure to the metal bumps.

An embodiment of the present application provides a semiconductor device, including a substrate, a chip, a latch-up protection circuit, and a redistribution layer. The chip is on the substrate. The latch-up protection circuit is separated from the chip in a direction. The redistribution layer transmits a signal between the latch-up protection circuit and the chip.

A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.