Heat sink and heat sink arrangements are provided for an electronic device immersed in a liquid coolant. A heat sink may comprise: a base for mounting on top of a heat-transmitting surface of the electronic device and transferring heat from the heat-transmitting surface; and a retaining wall extending from the base and defining a volume. A heat sink may have a wall arrangement to define a volume, in which the electronic device is mounted. A heat sink may be for an electronic device to be mounted on a surface in a container, in an orientation that is substantially perpendicular to a floor of the container. Heat is transferred from the electronic device to liquid coolant held in the heat sink volume. A cooling module comprising a heat sink is also provided. A nozzle arrangement may direct liquid coolant to a base of the heat sink.

An apparatus is described. The apparatus includes a cold plate. The ruler factor cold plate is to receive heat from semiconductor chips of a electronic component that is to be plugged into an electronic system. The cold plate has at least one of: a) a linearly advancing physical interface, the linearly advancing physical interface to make physical contact with a corresponding linearly advancing physical interface of a cooling component of the electronic system, the physical contact to create a thermal path from the cold plate to the cooling component; b) first fingers on a first face of the cold plate to make spring-force thermal contact with the semiconductor chips of the electronic component and second fingers on an opposite second face of the cold plate to make spring-force thermal contact with the respective semiconductor chips of another, neighboring electronic component.

An apparatus for use in testing an integrated circuit semiconductor wafer device under test (wafer DUT) includes a probe configured to probe a surface of the wafer DUT during testing thereof, a thermal interposer (TI) including a heater layer arranged with a plurality of zones corresponding to a plurality of areas of the wafer DUT, the TI configured to come into proximity to a surface of the wafer DUT and further configured to selectively heat the plurality of areas by selectively heating the plurality of zones, the heater layer including a plurality of heating elements configured to correspond to the plurality of zones, and a plurality of temperature measurement devices configured to correspond to the plurality of zones, a cold plate disposed in proximity to the TI and configured to selectively cool the plurality of areas of the wafer DUT, and a thermal controller configured to control selective cooling of the cold plate and configured to control selective heating of the plurality of heating elements of the TI during the testing.

A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A conductive layer is formed over the encapsulant and into the first trench.

A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A conductive layer is formed over the encapsulant and into the first trench.

A semiconductor device, including: a stacked substrate; a semiconductor device element mounted on the stacked substrate via a first bonding layer; a metal base bonded to the stacked substrate via a second bonding layer, the metal base having two ends and a center portion; and a water jacket bonded to the metal base. The first and second bonding layers are identical, or different, in a material and a composition thereof. The metal base has a plurality of heat dissipation fins, lengths of which are in an ascending order from each of the ends to the center portion of the metal base.

A semiconductor device, including: a stacked substrate; a semiconductor device element mounted on the stacked substrate via a first bonding layer; a metal base bonded to the stacked substrate via a second bonding layer; and a water jacket bonded to the metal base, the water jacket having two ends and a center portion. The first and second bonding layers are identical, or different, in a material and a composition thereof. The water jacket has a plurality of heat dissipation fins, lengths of which are in an ascending order from each of the ends of the water jacket to the center portion of the water jacket.

Consistent with the present disclosure, a scalable high density package is provided in which peripheral devices are provided within the same footprint or area as core logic, e.g., switching circuitry by providing the peripheral devices can be placed on the top or bottom of one or more core-I/O chips. In addition, a liquid cooled heatsink may be provided, in one example, between the core-I/O chips and the peripheral devices. A substrate, such as a printed circuit board may also be provided, such that the core-I/O chips and heatsink are provided on one side of the substrate and power supplies are provided on the other side. Conductors provided in vias that extend through the heatsink deliver power, such as a current, to the core-VO chips and the peripheral devices. Each of the foregoing circuits, therefore, is provided in a vertical arrangement to thereby provide reduce the size of the package.

The invention relates to a computer-implemented method for determining a manufacturable cooling structure for cooling a semiconductor device wherein the method receives as input at least i) physical parameters of the semiconductor device, wherein the physical parameters are related to physical properties of the semiconductor device, and ii) an array of numbers (1) indicative of a spatial power distribution of the semiconductor device, wherein the method comprises the following steps: 1) determining, using an topology optimization algorithm, a cooling structure based on the received input, and 2) providing, as output, a filetype containing the determined cooling structure in a data format based on which the determined cooling structure can be physically manufactured, wherein the filetype containing the determined cooling structure is a vector-based filetype). There is further provided a semiconductor device formed using the method of the invention and a corresponding electronic design automation tool.

A structure is disclosed. The structure can include a first processor die, a second processor die, a first memory unit, and a connecting element. The second processor die can be laterally spaced from the first processor die. The first memory unit can be disposed vertically above the first processor die. The connecting element can be disposed vertically to the first processor die and the second processor die. The connecting element can include a conductor electrically connecting the first processor die and the second processor die.