Abstract
The invention relates to a computer-implemented method for determining a manufacturable cooling structure for cooling a semiconductor device wherein the method receives as input at least i) physical parameters of the semiconductor device, wherein the physical parameters are related to physical properties of the semiconductor device, and ii) an array of numbers (1) indicative of a spatial power distribution of the semiconductor device, wherein the method comprises the following steps: 1) determining, using an topology optimization algorithm, a cooling structure based on the received input, and 2) providing, as output, a filetype containing the determined cooling structure in a data format based on which the determined cooling structure can be physically manufactured, wherein the filetype containing the determined cooling structure is a vector-based filetype). There is further provided a semiconductor device formed using the method of the invention and a corresponding electronic design automation tool.
Claims
1-31. (canceled)
32. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to: identify a spatial power distribution map of a semiconductor device; determine an original cooling structure for the semiconductor device based on the spatial power distribution map, wherein the original cooling structure includes fluid channels; execute a simulation based on the original cooling structure, wherein the simulation evaluates metrics including at least pressure drop and thermal resistance; change at least one parameter of the original cooling structure based on the simulation to generate an adjusted cooling structure; and select the adjusted cooling structure as a final cooling structure.
33. The at least one non-transitory computer readable storage medium of claim 32, wherein the spatial power distribution map is a grid representing one or more of heat flux or average power dissipation per cell of the grid.
34. The at least one non-transitory computer readable storage medium of claim 32, wherein to determine the original cooling structure, the instructions, when executed, further cause the computing system to: determine a position of an inlet of the original cooling structure.
35. The at least one non-transitory computer readable storage medium of claim 32, wherein to determine the original cooling structure, the instructions, when executed, further cause the computing system to: determine a position of an outlet of the original cooling structure.
36. The at least one non-transitory computer readable storage medium of claim 32, wherein the instructions, when executed, further cause the computing system to: transmit a design of the final cooling structure to a manufacturer in a file format for manufacturing of the final cooling structure.
37. The at least one non-transitory computer readable storage medium of claim 32, wherein the instructions, when executed, further cause the computing system to: manufacture at least one thermal element in or on an outer surface of a heat-generating component according to the final cooling structure.
38. The at least one non-transitory computer readable storage medium of claim 32, wherein the semiconductor device produces non-uniform heat distribution.
39. The at least one non-transitory computer readable storage medium of claim 32, wherein to determine the original cooling structure, the instructions, when executed, further cause the computing system to: execute a machine learning process based on the spatial power distribution map.
40. The at least one non-transitory computer readable storage medium of claim 32, wherein to determine the original cooling structure, the instructions, when executed, further cause the computing system to: determine the original cooling structure based on physical parameters including one or more of dimension parameters of the semiconductor device, material properties of a die of the semiconductor device, material properties of a cooling fluid of the original cooling structure, material properties of the original cooling structure or material properties of a chip of the semiconductor device.
41. The at least one non-transitory computer readable storage medium of claim 32, wherein the instructions, when executed, further cause the computing system to: identify a temperature of the semiconductor device; and convert the temperature into the spatial power distribution map.
42. The at least one non-transitory computer readable storage medium of claim 32, wherein the spatial power distribution map includes distinct spatial power distribution maps that represent different operating conditions.
43. The at least one non-transitory computer readable storage medium of claim 32, wherein the spatial power distribution map is a transient spatial power distribution map.
44. The at least one non-transitory computer readable storage medium of claim 32, wherein to determine the original cooling structure, the instructions, when executed, further cause the computing system to: identify a symmetry in the spatial power distribution map; determine an axis of the symmetry; and reduce the spatial power distribution map to an area defined by the axis of the symmetry.
45. The at least one non-transitory computer readable storage medium of claim 32, wherein the semiconductor device is a 2.5-dimensional semiconductor device.
46. The at least one non-transitory computer readable storage medium of claim 32, wherein the original cooling structure includes multiple microfluidic cooling structure layers that are adjusted to generate the adjusted cooling structure.
47. The at least one non-transitory computer readable storage medium of claim 32, wherein the instructions, when executed, further cause the computing system to: identify a constraint; and add the constraint to the spatial power distribution map.
48. The at least one non-transitory computer readable storage medium of claim 47, wherein the constraint is a maximum pressure drop.
49. The at least one non-transitory computer readable storage medium of claim 47, wherein the constraint is a minimum distance between adjacent walls.
50. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to: identify physical parameters including one or more of dimension parameters of a semiconductor device, material properties of a die of the semiconductor device, material properties of a cooling fluid of an original cooling structure, material properties of the original cooling structure or material properties of a chip of the semiconductor device; determine a design for the original cooling structure based on a spatial power distribution map and the physical parameters, wherein the original cooling structure includes fluid channels; execute a simulation based on the original cooling structure, wherein the simulation evaluates metrics including at least pressure drop and thermal resistance; change at least one parameter of the original cooling structure based on the simulation to generate an adjusted cooling structure; select the adjusted cooling structure as a final cooling structure; and manufacture at least one thermal element in or on an outer surface of a heat-generating component of the semiconductor device according to the final cooling structure.
51. A computing device comprising: a processor; and a memory coupled to the processor, the memory including a set of instructions, which when executed by the processor, cause the processor to: identify a spatial power distribution map of a semiconductor device; determine an original cooling structure for the semiconductor device based on the spatial power distribution map, wherein the original cooling structure includes fluid channels; execute a simulation based on the original cooling structure, wherein the simulation evaluates metrics including at least pressure drop and thermal resistance; change at least one parameter of the original cooling structure based on the simulation to generate an adjusted cooling structure; and select the adjusted cooling structure as a final cooling structure.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0055] Exemplar embodiments of the invention are disclosed in the description and illustrated by the drawings in which:
[0056] FIG. 1 schematically illustrates an embodiment of the method for determining a manufacturable cooling structure for cooling a semiconductor device during operation;
[0057] FIG. 2 schematically illustrates a microfluidic cooling structure with a separately designed manifold;
[0058] FIG. 3 schematically illustrates a microfluidic cooling structure which is jointly designed with a manifold;
[0059] FIG. 4 schematically illustrates a method according to the invention;
[0060] FIG. 5 schematically illustrates a semiconductor device with a cooling structure provided on a separate die;
[0061] FIG. 6 schematically illustrates an overlay of a spatial power distribution map and a corresponding determined cooling structure;
[0062] FIG. 7 schematically illustrates a cross-section of a semiconductor device with an integrated microfluidic cooling structure determined using a method according to the first aspect of the present invention;
[0063] FIG. 8 schematically illustrates a multi-layer semiconductor device with a microfluidic cooling structure determined using a method according to the first aspect of the present invention;
[0064] FIG. 9 schematically illustrates a multi-layer semiconductor device, with a microfluidic cooling structure determined using a method according to the first aspect of the present invention, on a substrate;
[0065] FIG. 10 schematically illustrates a multi-layer semiconductor device on a substrate with additional chiplets on the substrate, with a microfluidic cooling structure determined using a method according to the first aspect of the present invention;
[0066] FIG. 11 schematically illustrates a multi-layer semiconductor device with multiple heat-generating elements, with a microfluidic cooling structure determined using a method according to the first aspect of the present invention;
[0067] FIG. 12 schematically illustrates a multi-layer semiconductor device with a plurality of microfluidic layers, with the microfluidic cooling structure determined using a method according to the first aspect of the present invention; and
[0068] FIG. 13 schematically illustrates a cross-section of a chip separated from a microfluidic cooling structure, with the microfluidic cooling structure determined using a method according to the first aspect of the present invention, by an intermediate thermal interface.
DETAILED DESCRIPTION OF THE DRAWINGS
[0069] FIG. 1 schematically illustrates an embodiment of the computer-implemented method for determining a manufacturable cooling structure for cooling a semiconductor device during operation. The method receives as input an array of numbers 1 indicative of a spatial power distribution of the semiconductor device. This array of numbers 1 is converted to a spatial power distribution map 1. Constraints 2 may be added to the spatial power distribution map 1, which constraints are schematically illustrated by four black dots and the black stripes around the circumference of the drawing in FIG. 1. Inlets/outlets 3 of a manifold are schematically indicated by the striped rectangles in FIG. 1. Through these inlets/outlets 3, cooling liquid enters asubsequently determinedcooling structure. In the embodiment of FIG. 1, it is assumed that the positions for inlets/outlets 3 are pre-determined. Next, potential symmetries 4 in the spatial power distribution map are determined. Such symmetries 4 may often arise in practice as integrated circuits, for example, often comprise repetitions of base circuit elements. Recognizing symmetries may help in simplifying computations for determining a cooling structure. In the embodiment of FIG. 1, for example, two axes of symmetry are shown, and the determining of the cooling structure may be carried out for only one of the four shown quadrants, i.e., for a reduced domain 5. (Simulated) cooling behaviour of the determined cooling structure 6 on the part of the semiconductor device corresponding to the reduced domain 5 is visualised as a temperature map 7, and design validation 8 typically takes place thereafter. If the cooling behaviour of the determined cooling structure 6 is determined sufficient, for example, the entire cooling structure 6 may be determined by exploiting previously determined symmetries and boundary conditions. The cooling structure 6 is provided in a file format suitable for manufacturing. The manufactured cooling structure 9 may be used for cooling the semiconductor device to which it is adapted.
[0070] FIG. 2 schematically illustrates a microfluidic cooling structure with a separately designed manifold. The geometry of the microfluidic channels of the cooling structure 6 may be the result of a 2D/2.5D topology optimization and the inlet manifold 3 and outlet manifold 3 of the cooling system is determined by a 3D topology optimization with fixed feeding/extraction openings. In this case, the problems of cooling structure design and manifold design are independent in the sense that their topology optimization can run parallelly since their common interface (the aforementioned openings) has an a priori fixed geometry and position.
[0071] FIG. 3 schematically illustrates a microfluidic cooling structure which is jointly designed with a manifold. Both the channels of the cooling structure 6 and the inlet manifold 3 and outlet manifold 3 of the cooling system are the results of a joint 3D topology optimization with free feeding/extraction openings for the manifolds. Two different geometry parametrizations may be used, one for the cooling structure and one for the manifolds, allowing the manufacturing of each individual component. The advantage of this decomposition of the topology optimization in 2D channels and 3D inlet-outlet manifolds is that optimization of the 2D channels uses the entire physics equations (Navier-Stokes equations and heat transfer equations) while optimization of the 3D inlet-outlet manifolds uses only the Navier-Stokes equations; these decomposed topology optimizations are therefore coupled to let the optimization algorithm design a more optimized geometry compared to a separate design of manifolds and cooling structure.
[0072] FIG. 4 schematically illustrates a method according to the invention. The method receives as input 10 at least i) physical parameters of the semiconductor device, wherein the physical parameters are related to physical properties of the semiconductor device, and ii) an array of numbers indicative of a spatial power distribution of the semiconductor device, determines 11 a cooling structure based on the received input 10, and provides as output 12 the determined cooling structure in a file format/data format suitable for manufacturing.
[0073] FIG. 5 schematically illustrates a semiconductor device with a cooling structure provided on a separate die. Device logic 13 of the semiconductor device is provided on a first die and the manufactured cooling structure 9 is provided on a second die. The second die can be bonded or attached to the first die to enable cooling of the device logic 13, e.g., embodied as an integrated circuit. Alternatively, both device logic and cooling structure may share one die, being provided on opposite sides of the one die.
[0074] FIG. 6 schematically illustrates an overly of a spatial power distribution map received as input and the corresponding determined (optimized) cooling structure provided as output of the method according to the first aspect of the present invention. The numbers in the legend of FIG. 6 are related to heat flux with units of Watt per square millimetre. Regions with higher heat flux have more narrow channels to provide more surface area and therefore heat transfer, while colder regions with smaller heat flux have wider channels to let the cooling liquid flow through with a lower pressure difference. The left panel schematically illustrates a low Reynolds number (viscous) case, while the right panel a high Reynolds (inertial) case. For the latter, the produced fins are shorter in the streamwise direction and the flow follows a rather more curved flow pattern, while for the former, the produced fins are longer in the streamwise direction and the flow follows a rather straighter flow pattern. The evident visual differences between the two optimized channel geometries demonstrate clearly the need for a custom design, tailored to every different application.
[0075] FIG. 7 schematically illustrates a cross-section of a semiconductor device with an integrated microfluidic cooling structure. The semiconductor device can be modelled as a 2-layer system with an integrated microfluidic cooling structure layer 25 and solid material layer 14. Together, these two layers represent the total thickness 14 of the semiconductor device. Power is dissipated on the opposite side of the microfluidic cooling structure layer in the active region of the semiconductor device comprising device logic 13. The microfluidic cooling structure layer comprises voids 9 where fluid can pass through and solid regions 9. The determination of the optimal distribution of voids and solid regions is performed by a method according to the first aspect of the present invention.
[0076] FIG. 8 schematically illustrates a multi-layer semiconductor device. In addition to the active region 13 of the semiconductor device which is modelled in the embodiment of FIG. 7, redistribution layers (RDL) 15 may be modelled as well. The RDL layers comprise multiple conductive and/or dielectric elements 16, 16, 16, 16. Each layer can either have uniform material properties 16 or non-uniform properties 16, 16, 16. Layers can have vias extending through the layer 17, 17, as well as lateral metallic traces 18. Each component in this multi-layer system and the complete structure of RDL layers 15 can be modelled with their respective material properties to form an extended conduction model, to capture the conduction of heat close to the heat source (e.g., the device logic 13) more accurately, and thereby improve cooling structure determination by a method according to the first aspect of the present invention.
[0077] FIG. 9 schematically illustrates a multi-layer semiconductor device on a substrate. The shown multi-layer semiconductor device corresponds to the embodiment shown in FIG. 8. Solder bumps 19 and the underlying substrate 20 are also considered (as part of an extended conduction model) during the determining of the cooling structure by a method according to the first aspect of the present invention. The substrate 20 may be a printed circuit board (PCB) or an interposer. Additional heterogeneity such as layers with varying material properties 21, 21 within the substrate 20 can be included during the determining of the cooling structure.
[0078] FIG. 10 schematically illustrates a multi-layer semiconductor device on a substrate with additional chiplets on the substrate. In addition to the multi-layer structure shown in FIG. 9, additional chiplets 22, 22 are considered during the determining of the cooling structure by a method according to the first aspect of the present invention. These chiplets can, for example, be memory dies which are laterally positioned next to the central computing die. These chiplets may be modelled with the same level of granularity and layers as described in FIGS. 7 to 9. In addition, the power dissipation in these chiplets may also be included in the optimization method of the method according to the first aspect of the present invention. In addition, a microfluidic cooling may be integrated inside these chiplets as well, or alternatively, a fixed heat transfer coefficient may be assumed on the top surface 23, 23 of the chiplets 22, 22 to mimic a conventional heat sink or cold plate positioned on top of the chiplets.
[0079] FIG. 11 schematically illustrates a multi-layer semiconductor device with multiple elements of heat-generating elements. In contrast to the embodiments of FIGS. 7 to 10, in FIG. 11 multiple layers 15, 15, 15, 15 of heat-generating elements 24, 24, 24, 24 are stacked. A conduction model used by the method according to the first aspect of the present invention can be extended to include these multiple layers 15, 15, 15, 15. During optimization carried out by the method according to the first aspect of the present invention, temperature on all the multiple heat-generating layers may be considered in a loss function, and the design of the microfluidic cooling structure may be optimized to minimize the temperature of each heat-generating layer in the multi-layer stack shown in FIG. 11.
[0080] FIG. 12 schematically illustrates a multi-layer semiconductor device with a plurality of microfluidic layers. Differing from the embodiment shown in FIG. 11, multiple microfluidic cooling structure layers 25, 25, 25, 25 are vertically stacked in-between heat-generating elements. The method according to the first aspect of the present invention may simultaneously optimize the shape of the multiple microfluidic cooling structure layers 25, 25, 25, 25 based on the power dissipation (spatial power distribution map(s)) and correspond temperature of multiple heat-generating layers. Constraints 2 may be included for the positioning of solid material in the microfluidic layers such as vias 17 that pass through a solid layer 17 to provide electrical connection between the multiple layers.
[0081] FIG. 13 schematically illustrates a cross-section of a chip separated from a microfluidic cooling structure by an intermediate thermal interface. The chip 26 of the semiconductor device can be a single-layer chip or a multi-layer chip. The chip 26 is separated from the microfluidic cooling structure 9 with an intermediate thermal interface 27. A method according to the first aspect of the present invention may consider may consider both the chip 26 and the thermal interface 27 in order to determine an optimal shape of cooling channels of the cooling structure 9.
[0082] Various modifications and variations to the described embodiments of the invention will be apparent to those skilled in the art without departing from the scope of the invention as defined in the appended claims. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiment.
