A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

A semiconductor package includes a redistribution substrate, a chip stack structure disposed on the redistribution substrate and including a plurality of semiconductor chips disposed in a stack, a vertical wiring portion connecting the chip stack structure to the redistribution substrate and including a plurality of vertical wires that extend in a direction perpendicular to an upper surface of the redistribution substrate, a sealing member configured to seal at least a portion the chip stack structure and the vertical wiring portion, and a heat dissipation metal member disposed on side surfaces and an upper surface of the sealing member.

A microelectronic device includes a control logic structure including a high-power component. The microelectronic device also includes a memory array structure vertically offset from and attached to the control logic structure, the memory array structure comprising an array of memory cells. The microelectronic device further includes a heat sink structure vertically underlying and horizontally overlapping the high-power component, the heat sink structure comprising a material having higher thermal conductivity than semiconductor material of the control logic structure.

A bonded structure is disclosed. The bonded structure can include a substrate. The bonded structure can include a first memory unit disposed on the substrate. The first memory unit can have a first stack of memory dies and a first logic controller disposed on the first stack. The first logic controller can manage data communicated to or from the first stack of memory dies. The bonded structure can also include a processor die hybrid bonded to the first memory unit along a bonding interface and a vertical interconnect connecting the substrate to the processor die. The bonded structure can further include a second memory unit disposed on the substrate. The second memory unit can include a second stack of memory dies and a second logic controller disposed on the second stack. The second logic controller can manage data communicated to or from the second stack of memory dies.

Semiconductor devices having integrated cooling systems, and associated systems and methods, are disclosed herein. An example of a semiconductor device according to the present technology is a system-in-package device that includes a base substrate, a processing device and a high-bandwidth memory device that are each integrated with the base substrate, and a package cooling device that is thermally coupled to the processing device and the high-bandwidth memory device. In some embodiments, the package cooling device includes a first heat spreader thermally coupled to an upper surface of the processing device, a second heat spreader thermally coupled to an upper surface of the high-bandwidth memory device, a thermoelectric cooling device positioned between and thermally coupled to a portion of the first heat spreader and the second heat spreader, and a heat exchanger thermally coupled to the first heat spreader.

A semiconductor device includes: a wiring board having a surface; a chip stack disposed above the surface and including a first semiconductor chip; a second semiconductor chip disposed between the surface and the chip stack; a spacer disposed between the surface and the first semiconductor chip, the spacer surrounding the second semiconductor chip along the surface, and the spacer containing a material higher in thermal conductivity than silicon; and a sealing insulation layer covering the chip stack.

A stacked semiconductor device includes a base semiconductor die and a plurality of core semiconductor dies that are stacked in a vertical direction, a plurality of temperature sensing circuits included in the plurality of core semiconductor dies, respectively, a conversion circuit included in the base semiconductor die, and a plurality of vertical conductive paths electrically connecting the base semiconductor die and the plurality of core semiconductor dies, through silicon vias provided in the plurality of vertical conductive paths in the vertical direction. The plurality of temperature sensing circuits generate sensing voltages that vary according to operating temperatures, and transfer the sensing voltages to the conversion circuit through a first vertical conductive path among the plurality of vertical conductive paths. The conversion circuit converts the sensing voltages into a temperature code.

A high bandwidth memory according to an example embodiment may include a base die, and a semiconductor stack on the base die. The semiconductor stack may include a plurality of semiconductor dies, which may be stacked in a vertical direction. Each of the plurality of semiconductor dies may include a plurality of memory dies arranged in a horizontal direction.

Semiconductor devices having integrated cooling systems, and associated systems and methods, are disclosed herein. An example of a semiconductor device according to the present technology is a system-in-package device that includes a base substrate, a processing device and a high-bandwidth memory device that are each integrated with the base substrate, and a package cooling device that is thermally coupled to the processing device and the high-bandwidth memory device. In some embodiments, the package cooling device includes a first heat spreader thermally coupled to an upper surface of the processing device, a second heat spreader thermally coupled to an upper surface of the high-bandwidth memory device, a thermoelectric cooling device positioned between and thermally coupled to a portion of the first heat spreader and the second heat spreader, and a heat exchanger thermally coupled to the first heat spreader.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.