A semiconductor device includes a gate structure on a substrate, a contact etch stop layer (CESL) on the gate structure, an interlayer dielectric (ILD) layer on the CESL, a first contact plug in the ILD layer and adjacent to the gate structure, a first stop layer on the ILD layer, an inter-metal dielectric (IMD) layer on the first stop layer, a first metal interconnection in the IMD layer, and an air gap around the gate structure and exposing the CESL and the first metal interconnection.

It is possible to improve characteristics of a film formed on a substrate. There is provided a technique that includes: (a) forming a film by supplying a first source gas and a reactive gas to a substrate; and (b) etching at least a part of the film by supplying a second source gas and the reactive gas to the substrate after (a).

Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

A semiconductor device includes a lower insulating film that includes a first and second trenches on a substrate, a first wiring in the first trench, a second wiring in the second trench, a capping insulating film including an insulating recess portion and an insulating liner portion, an upper insulating film on the capping insulating film, and an upper contact that penetrates the capping insulating film and connects to the first wiring, The insulating recess portion is in the second trench and the insulating liner portion extends along an upper surface of the lower insulating film. The upper contact includes a contact recess portion in the first trench, an extended portion connected to the contact recess portion, and a plug portion connected to the extended portion inside the upper insulating film. A width of the extended portion is greater than a width of the plug portion.

A method of providing access to a contact pad located on a base polyimide layer of an electronic part comprises (i) covering the contact pad and the base polyimide layer with a cover layer comprised of a metallic mask layer, a polyimide layer, and an adhesive layer. The adhesive layer attaches the cover layer to the contact pad and the base polyimide layer. The metallic mask layer is exposed. The method further includes (ii) removing a portion of the metallic mask layer of the cover layer directly above the contact pad, and (iii) through the removed portion of the metallic mask layer, using a plasma-etching process to create an access opening to the contact pad through the polyimide layer and the adhesive layer.

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

Provided is a conductive structure and a method for forming such a structure. The method includes forming a treatable layer by depositing a layer comprising a metal over a structure; performing a directional treatment process on a targeted portion of the treatable layer to convert the targeted portion to a material different from a non-targeted portion of the treatable layer, wherein the directional treatment process is selected from the group consisting of nitridation, oxidation, chlorination, carbonization; and selectively removing the non-targeted portion from the structure, wherein the targeted portion remains over the structure.

A method of manufacturing a semiconductor device comprises forming a preliminary substrate insulating layer on a lower substrate region; forming buried interconnection lines on the preliminary substrate insulating layer; forming a substrate insulating layer on the buried interconnection lines; forming an upper substrate region on the lower substrate region to form a substrate; forming active regions and a device isolation layer by removing a portion of the substrate; forming sacrificial gate structures and source/drain regions; removing the sacrificial gate structures; forming gate structures; forming a first interlayer insulating layer on the gate structures; forming first contact holes to expose the buried interconnection lines; forming preliminary lower contact plugs by filling the first contact holes; forming lower contact plugs; forming second contact holes to expose a portion of the source/drain regions or a portion of the gate structures; and forming upper contact plugs by filling the second contact holes.