The present invention provides a silicon nitride sintered substrate capable of reducing contamination caused by a boron nitride powder or the like used as a releasing agent and problems in bonding strength and dielectric strength at the time of laminating metal layers or the like, where the contamination is caused by a network structure provided by a silicon nitride crystal formed on the surface of the substrate in an unpolished state after sintering a silicon nitride powder. The silicon nitride substrate in an unpolished state after sintering is a silicon nitride sintered substrate where a cumulative volume of pores having a diameter in a range of 1 to 10 m is not more than 7.010.sup.5 mL/cm.sup.2 in a measurement by a mercury porosimetry. Preferably, Ra of the surface is not more than 0.6 m and arithmetic mean peak curvature (Spc) of a peak is not more than 4.5 [1/mm].

Disclosed in the present invention is a rare-earth doped semiconductor material. Compounds of two rare-earth elements R and R having different functions are introduced into an indium oxide containing material. The coupling of R element ions to an O2p orbit can effectively enhance the transfer efficiency of the rare-earth R as a photogenerated electron transfer center, such that the light stability of a device with a small amount of R doping can be achieved. Compared with single rare-earth element R doping, due to less doping, the impact on a mobility is less, such that higher mobility and light stability devices can be obtained. Further provided in the present invention is a semiconductor-based thin-film transistor, and an application.

A method includes forming a package substrate comprising forming through-openings in a glass substrate, filling the through-openings to form through-vias in the glass substrate, forming a first interconnect structure underlying the glass substrate, and forming a second interconnect structure overlying the glass substrate. The method further includes forming an interposer over the package substrate, and bonding package components over and electrically connected to the package substrate through the interposer.

A system comprises: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power switch including a drain terminal, a source terminal, and a gate terminal; and a controller configured to detect a change in current at the source terminal of the power switch using a complex impedance of a metal trace connected to the source terminal of the power switch, and control a gate control signal to the gate terminal based on the detected change in current.

An integrated device package is disclosed. The integrated device package can include a carrier that has a multilayer structure having a first layer and a second layer. The first layer at least partially defines a lower side of the carrier. An electrical resistance of the second layer is greater than an electrical resistance of the first layer. The integrated device package can include a microelectronicmechanical systems die that is mounted on an upper side of the carrier opposite the lower side. The integrated device package can include a lid that is coupled to the carrier. The lid and the microelectronicmechanical systems die are spaced by a gap defining a back volume.

Embodiments disclosed herein include an electronic package that comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass. In an embodiment, the electronic package further comprises an opening through the substrate from the first surface to the second surface, where the opening comprises a first end proximate to the first surface of the substrate, a second end proximate to the second surface of the substrate, and a middle region between the first end and the second end. In an embodiment, the middle region has a discontinuous slope at junctions with the first end and the second end.

Implementations described herein relate to various semiconductor device assemblies. In some implementations, an apparatus includes a dielectric layer having a first material that is an insulative material, a conductive layer having a second material that is a conductive material, and a stimulus-responsive strain layer having a third material that deforms in response to an applied stimulus.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a first dielectric layer, at least one antenna, at least one die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive circuits, a third dielectric layer, a plurality of second conductive circuits, and an outer protective layer is provided. The first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. The die is electrically connected with the antenna. The die is electrically connected to the outside through bonding pads around a chip area on a second surface of the die. Thereby the FOWLP unit is formed and problems of the FOWLP module or technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

A power module includes: a first substrate having an outer surface and an inner surface; a semiconductor die coupled to the inner surface of the first substrate; a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate; and a first electrically conductive spacer coupled to inner surface of the first substrate and to the inner surface of the second substrate.

An integrated circuit package structure is provided. The integrated circuit package structure includes a circuit substrate. The circuit substrate includes a core, a first inorganic dielectric layer, an organic dielectric layer and a solder mask layer. The core has a first surface and a second surface opposite each other. The first inorganic dielectric layer is disposed on the first surface of the core. The organic dielectric layer is disposed on the second surface of the core. The solder mask layer is disposed on the organic dielectric layer. The solder mask is separated from the first inorganic dielectric layer by the organic dielectric layer and the core.