A glass which satisfies formulas (1) and (2), where a liquid phase temperature is denoted by T.sub.L ( C.), a Young's modulus calculated based on the composition is denoted by E (GPa), and a linear thermal expansion coefficient is denoted by (ppm/ C.),

[00001]$\begin{array}{cc}13.1E+9-T_{L}0& \left(1\right)\end{array}$$\begin{array}{cc}1923-156-T_{L}0.& \left(2\right)\end{array}$

A substrate includes a ceramic tile and a three-dimensional (3D) conductive structure. The 3D conductive structure includes a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, and a block disposed above the planar base layer. The block is monolithically integrated with the planar base layer. A top surface of the block is configured as a die attach pad. The planar base layer has a base vertical thickness from the top surface of the ceramic tile to a top surface of the planar base layer. The block and the planar base layer have a combined vertical thickness from the top surface of the ceramic tile to a top surface of the block that is greater than the base vertical thickness.

A method of forming a semiconductor package includes providing a metal lead frame comprising a die pad and a plurality of leads, mounting a high-voltage die on an upper surface of the die pad such that a load terminal of the high-voltage die is electrically connected to the die pad, mounting an electrical isolation pad on the die pad, and mounting a low-voltage die on the electrical isolation pad, wherein at least one of: mounting the high-voltage die, mounting the electrical isolation pad, and mounting the low-voltage die includes performing a float-limiting attachment process, wherein the float-limiting attachment process comprises performing a surface roughening process to an attachment surface that forms a border of roughened surface around a mounting area, arranging an attachment material within the mounting area with a mounting element disposed thereon, and liquifying the attachment material with the mounting element disposed thereon.

A semiconductor device includes a circuit substrate, a first semiconductor element, a second semiconductor element, and a connection element. The circuit substrate includes a first pad. The first semiconductor element is disposed on the circuit substrate and includes a second pad and a third pad. The second semiconductor element is disposed on the circuit substrate. The connection element is disposed on the circuit substrate and electrically connects the first semiconductor element and the second semiconductor element. The connection element includes a fourth pad. The second pad is bonded to the first pad through a conductive material, and the third pad is directly bonded to the fourth pad.

A substrate structure includes a first substrate and a second substrate bonded thereon. The first substrate includes a first dielectric substrate, a first conductive via, a first bonding layer, and a first electroless metal block. The first bonding layer has a first opening exposing the first conductive via, and the first electroless metal block is positioned within the first opening. The second substrate includes a second dielectric substrate, a second conductive via, a second bonding layer, and a second electroless metal block. The second bonding layer has a second opening exposing the second conductive via, and the second electroless metal block is positioned within the second opening. The second bonding layer is bonded to the first bonding layer to define a non-metal contact interface. The second electroless metal block is bonded to the first electroless metal block to define a metal bonding contact interface.

An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first sidewall and a second portion that includes a second sidewall, wherein the first sidewall includes seed metallization and the second sidewall excludes the seed metallization.

A packaging substrate according to the present disclosure comprises a core layer; a first conductive layer, which is a conductive layer disposed in contact with an upper surface of the core layer; and an adhesion reinforcement layer disposed on the core layer and surrounding at least a portion of the first conductive layer. The adhesion reinforcement layer comprises any one selected from the group consisting of a silicon-based compound, an acrylic-based compound, and a combination thereof. An arithmetic average roughness (Ra) value of the upper surface of the first conductive layer is 150 nm or less.

In this case, it is possible to effectively improve the adhesion strength of the insulating layer to the first conductive layer without excessively roughening the first conductive layer.

A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

Provided are a substrate, a method for preparing the substrate, an integrated passive device, and an electronic apparatus. The method for preparing the substrate includes: providing a base substrate including at least one blind via, wherein the base substrate includes a first surface and a second surface disposed oppositely, a blind via extends from a first surface side to interior of the base substrate, and an aperture of the blind via gradually decreases in a direction from the first surface to the second surface; forming a connection electrode in the blind via; thinning the base substrate along a direction from the second surface to the first surface, wherein the blind via on the thinned base substrate forms a via hole penetrating the base substrate.

Provided are a substrate, a method for preparing the substrate, an integrated passive device, and an electronic apparatus. The method for preparing the substrate includes: providing a base substrate including at least one blind via, wherein the base substrate includes a first surface and a second surface disposed oppositely, a blind via extends from a first surface side to interior of the base substrate, and an aperture of the blind via gradually decreases in a direction from the first surface to the second surface; forming a connection electrode in the blind via; thinning the base substrate along a direction from the second surface to the first surface, wherein the blind via on the thinned base substrate forms a via hole penetrating the base substrate.