A semiconductor device includes a support member, a semiconductor element and a sealing member. The semiconductor element is disposed on a first side in a thickness direction relative to the support member. The sealing member covers a part of the support member and the semiconductor element. The support member has a first surface facing a second side in the thickness direction and exposed from the sealing member. The first surface is formed with a first uneven region. In an example, the first uneven region has an arithmetic mean roughness between 0.2 m and 13 m. In an example, the first uneven region includes a plurality of uneven lines in an arc shape.

An integrated circuit package includes a leadframe with leads delimiting a center cavity. The leads of the leadframe have upper surfaces with a surface texture or finish having a first surface roughness. A drop-in die pad is installed within the center cavity. The drop-in die pad has an upper surface with a surface texture or finish having a second surface roughness that is rougher than the first surface roughness. An integrated circuit die is mounted to the upper surface of the drop-in die pad and electrical connections are formed between bonding pads of the integrated circuit die and the leads of the leadframe. An encapsulation body encapsulates the leadframe, drop-in die pad and electrical connections.

An example lead-frame package, a method of manufacturing the lead-frame package, and an electrical system comprising the lead-frame package utilizing an integrated insulating layer to electrically insulate an integrated circuit within the lead-frame package from one or more electrical components are provided. The example lead-frame package includes an integrated circuit substrate and an integrated circuit. An integrated insulating layer forms a first surface of the integrated circuit substrate. A plurality of conductive leads provides a conductive path between a second surface of the integrated circuit substrate and the first surface, with a conductive trace formed within the integrated circuit substrate. The integrated insulating layer defines conductive wirebond pads providing an electrical connection to the plurality of conductive leads. In addition, the integrated circuit is electrically isolated from the conductive trace by the integrated insulating layer, wherein the integrated circuit is positioned to determine an electromagnetic property of the conductive trace.

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

A stacked transistor arrangement and process of manufacture thereof are provided. Switched electrodes of first and second transistor chips are accessible on opposite sides of the first and second transistor chips. The first and second transistor chips are stacked one on top of the other. Switched electrodes of adjacent sides of the transistor chips are coupled together by a conductive layer positioned between the first and second transistor chips. Switched electrodes on sides of the first transistor chip and the second transistor chip that are opposite the adjacent sides are coupled to a lead frame by bond wires or solder bumps.

An electronic device includes a non-conductive die attach film on a side of a conductive lead, a semiconductor die having a first side and a lateral side, the first side on the non-conductive die attach film, and the lateral side including striations, and a package structure enclosing the semiconductor die and a portion of the conductive lead. A method includes singulating portions of a non-conductive die attach film on a carrier, attaching a backside of a wafer to the singulated portions of the non-conductive die attach film, and singulating semiconductor dies of the wafer while the backside of the wafer is attached to the singulated portions of the non-conductive die attach film.

A microelectronic device package includes: a package substrate having a first set of leads spaced from a first die pad configured for mounting semiconductor devices, and a second set of leads spaced from a second die pad configured for mounting additional semiconductor devices, the first die pad and the first set of leads spaced from the second die pad and the second set of leads. Semiconductor devices are mounted to the first die pad and second die pad. A ceramic interposer is mounted to the package substrate in thermal contact with at least the first die pad. Mold compound covers the semiconductor devices, a portion of the ceramic interposer, and portions of the first set and the second set of leads.

In examples, a semiconductor package includes a solder joint pillar within a solder joint. The solder joint couples various structures of the semiconductor package.

An electronic device includes a leadframe, where the leadframe includes inner leads, external leads, and die attach portions. The leadframe has channels defined at a junction between the die attach portions and the inner leads, where the channel mitigates crack propagation along a path of the die attach portions. A die assembly is attached to the die attach portions and copper pillars are provided to connect the die assembly to the die attach portions. A mold compound encapsulates the die assembly, the inner leads, the die attach portions, and the copper pillars.

A method of forming a semiconductor device includes forming a base leadframe having a plurality of leads and a die pad. A cavity is formed in each lead of a set of leads of the plurality of leads. Bond pads of a first semiconductor die are interconnected with respective leads of the plurality of leads. A metal core connector is placed on each cavity of the set of leads. A packaged device is mounted on the base leadframe by way of the metal core connectors. The packaged device includes a second semiconductor die mounted on package leads of a package leadframe. A first encapsulant encapsulates the second semiconductor die and package leadframe. A portion of each of the package leads is exposed through the first encapsulant. A second encapsulant encapsulates the first semiconductor die, a portion of the base leadframe, and a portion of the packaged device.