A semiconductor device includes a field effect transistor having source/drain regions, the source/drain regions having a source/drain region width. Backside contacts are connected to the source/drain regions. The backside contacts have a dimension greater than the source/drain region width. Metal lines are connected to the backside contacts. The metal lines have a gap therebetween and include a metal line width. The metal lines further include metal line extensions that have an extension width that is less than the metal line width and extends beyond the metal line width to increase tip to tip distance between the metal lines while maintaining a pitch across the gap.

A semiconductor device according to one aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and extends in a direction forming an angle of 30 to 30 with respect to the first direction. A semiconductor device according to another aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and has a joint portion that is long in one direction in plan view and an angle of a long direction of the joint portion with respect to the first direction is 30 to 30.

A chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a dielectric stack under the gate, the dielectric stack including one or more first dielectric layers and one or more second dielectric layers.

Apparatus and methods to process one or more wafers are described. A spatial deposition tool comprises a plurality of substrate support surfaces on a substrate support assembly and a plurality of spatially separated and isolated processing stations. The spatially separated isolated processing stations have independently controlled temperature, processing gas types, and gas flows. In some embodiments, the processing gases on one or multiple processing stations are activated using plasma sources. The operation of the spatial tool comprises rotating the substrate assembly in a first direction, and rotating the substrate assembly in a second direction, and repeating the rotations in the first direction and the second direction until a predetermined thickness is deposited on the substrate surface(s).

A method includes forming a plurality of channel layers vertically stacked over a semiconductor substrate; forming a gate structure surrounding the channel layers; forming a first source/drain epitaxial structure on a first side of the channel layers; etching a first opening at least in the semiconductor substrate and the first source/drain epitaxial structure expose a backside of the first source/drain epitaxial structure; and forming an isolation plug in the first opening, wherein the isolation plug is at least laterally aligned with a bottommost one of the channel layers.

Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and an etch stop bilayer is formed on the silicon wafer. The insertion of an etch stop bilayer in the starting wafer will serve as an etch stop for deep trench formation on the wafer frontside and for wafer backside planarization. With this approach variations in the sacrificial material depth in a GAA device and substrate thickness may offer benefits in lithography overlay control.

The present invention relates to a method for manufacturing multi-pixel gas microsensors, wherein each multi-pixel gas microsensor comprises at least a first pixel group having a first sensing material and a second pixel group having a second sensing material different from the first material. The method comprises a first step of providing a wafer substrate and processing the wafer substrate for building a plurality of multi-pixel microsensors having first and second groups of pixels, a second step of selecting sensing materials for each of the groups of pixels, and a third step of activation of the first and the second pixel group by coating electrode pairs of the first and second pixel group with the corresponding sensing materials selected.

A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.

A semiconductor storage device including a two-port SRAM cell, in which nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.