A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.

A trench for a trench capacitor structure is formed using a metal-containing masking layer. The metal-containing masking layer enables the layers of a semiconductor device to be etched to form the trench in a manner that reduces and/or minimizes corner rounding at the top of the trench. In particular, the metal-containing masking layer suppresses etching in the corners at the top of the trench in that the metal masking-containing layer can be used for multiple etch operations and does not need to be removed between etch operations because of contamination concerns. This enables the metal-containing masking layer to be used to fully form the trench, which enables the metal-containing masking layer to protect the top of the trench from corner rounding.

According to an aspect of the present disclosure, a semiconductor device includes a cell structure including a gate stacking structure in a first region and an insulation structure in a second region, a first wiring portion disposed on a first surface of the cell structure, a second wiring portion disposed on a second surface of the cell structure opposite to the first surface, a channel structure at least partially penetrating the gate stacking structure and being electrically coupled with the first wiring portion and the second wiring portion, and a capacitor structure including a plurality of penetration structures. The gate stacking structure includes a plurality of gate electrodes while interposing an interlayer insulation layer therebetween. Each of the plurality of penetration structures at least partially penetrates at least a portion of the insulation structure.

A system that includes improved integrated circuit interconnects integrated with interconnect capacitors that reduce noise and improve signal quality is disclosed. The system comprises a first circuit board layer including a contact region of a conductor trace. The system further comprises a second layer including an interconnect capacitor, wherein the interconnect capacitor comprises a first side coupled over at least a portion of the contact region of the first circuit board layer to form a contact pad on a second side of the interconnect capacitor configured to interface with an integrated circuit chip.

A semiconductor device includes a capacitor having a first conductor plate, a second conductor plate, and a portion of a dielectric layer interposed therebetween. The semiconductor device includes a plurality of first contact structures in electrical contact with the first conductor plate. The semiconductor device includes a plurality of second contact structures in electrical contact with the second conductor plate. The plurality of first contact structures and the plurality of second contact structures are laterally arranged in a checkboard pattern, thereby causing each of the plurality of first contact structures to be surrounded by respective four of the plurality of second contact structures.

A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.

Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) device. The MIM device includes a first conductive layer disposed over a substrate, a first capacitor dielectric disposed over the first conductive layer, and a second conductive layer disposed over the first capacitor dielectric. The first conductive layer and the first capacitor dielectric laterally extend past an outermost sidewall of the second conductive layer. A second capacitor dielectric is disposed over the second conductive layer and the first capacitor dielectric, and a third conductive layer is disposed over the second capacitor dielectric. The third conductive layer laterally extends past the outermost sidewall of the second conductive layer. A conductive structure is coupled to both the first conductive layer and the third conductive layer. The conductive structure extends through the first capacitor dielectric and the second capacitor dielectric laterally outside of the second conductive layer.

A method for manufacturing a semiconductor device includes: forming a first interconnect structure over a substrate, the first interconnect structure including a first conductive feature; forming a resistor structure over the first conductive feature; forming a second interconnect structure on the resistor structure, the second interconnect structure including two second conductive features which are spaced apart from each other and which are electrically connected to the resistor structure; forming a third interconnect structure on the second interconnect structure, the third interconnect structure including two third conductive features which are spaced apart from each other and which are electrically connected to the two second conductive features, respectively; and forming a capacitor structure over the resistor structure such that the capacitor structure is disposed between the two third conductive features.

A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors between a first signal net and a second signal net. The integrated circuit includes multiple intermediate floating metal layers (or metal plates) formed between two signal nets. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit. At least one pair of floating metal layers have a via connection between them to reduce the overall insulating thickness of the resulting MIM capacitor.

An MIM capacitor structure includes a dielectric layer. An MIM capacitor body is disposed on the dielectric layer. The MIM capacitor body includes a first electrode and a second electrode stacked alternately and a capacitor dielectric layer disposed between the first electrode and the second electrode. The first electrode has a first extension part extending out from the MIM capacitor body. The second electrode has a second extension part extending out from the MIM capacitor body. The first extension part includes a first aluminum-containing material layer. The second extension part includes a second aluminum-containing material layer. A first conductive plug penetrates the first extension part, wherein the first conductive plug has a first arc which is concave toward the first aluminum-containing material layer. A second conductive plug penetrates the second extension part, wherein the second conductive plug has a second arc which is concave toward the second aluminum-containing material layer.