A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

Embodiments disclosed herein include an electronic package that comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass. In an embodiment, the electronic package further comprises an opening through the substrate from the first surface to the second surface, where the opening comprises a first end proximate to the first surface of the substrate, a second end proximate to the second surface of the substrate, and a middle region between the first end and the second end. In an embodiment, the middle region has a discontinuous slope at junctions with the first end and the second end.

A device package comprising an integrated cooling assembly comprising a semiconductor stack and a cooling channel, wherein the semiconductor stack comprises a first semiconductor device and a second semiconductor device stacked vertically above the first semiconductor device; and spacers extending between opposing surfaces of the first and second semiconductor devices to space the first semiconductor device away from the second semiconductor device, the spacers and the opposing surfaces of the first and second semiconductor devices collectively define the cooling channel therebetween; and the spacers comprise via electrically connecting the first semiconductor device and the second semiconductor device.

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

One example discloses a circuit package, including: wherein the circuit package is configured to include a circuit; a brick having a first set of vias and a second set of vias; wherein the first set of vias are configured to be filled with a first material; wherein a first end of the first material is configured to be electrically coupled to the circuit; wherein a second end of the material is configured to form an electrical terminal on an external surface of the circuit package; and wherein the second set of vias are configured to be filled with a second material different from the first material.

A semiconductor device including a redistribution substrate and a semiconductor chip on the redistribution substrate. The redistribution substrate includes an under-bump pad on a bottom surface of the redistribution substrate. The under-bump pad comprises a first pad part, a second pad part on the first pad part, and a via part that protrudes from the second pad part and contacts the first pad part. The first pad part has a first width in a first direction parallel to a top surface of the redistribution substrate. The second pad part has a second width in the first direction. The second width is greater than the first width.

A semiconductor device has a substrate and an electrical component disposed over the substrate. A heat spreader with a plasma-enhanced surface is disposed over the electrical component. A TIM is disposed between the electrical component and plasma-enhanced surface of the heat spreader. The TIM can be deposited on the electrical component or plasma-enhanced surface. The plasma-enhanced surface contains argon ions and oxygen ions. The heat spreader is disposed in a reaction chamber. Reactant gases, such as argon and oxygen, are introduced into the reaction chamber. An electric field is formed within the reaction chamber to ionize the argon and oxygen and form the plasma-enhanced surface. The plasma-enhanced surface has properties of roughness and tacky-ness or adhesive property by nature of the surface exhibiting a chemical bonding group. An underfill material is deposited between the electrical component and substrate. The electrical component can be a flipchip type semiconductor die.

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A method for manufacturing a semiconductor device comprises: forming isolation layers in a front surface of an upper wafer substrate; forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate; forming a first dielectric layer that fills the through hole; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer; and forming a second wiring line coupled to the through via.