A package structure is provided. The package structure includes a substrate including a cavity and a plurality of thermal vias connecting a bottom surface of the cavity to a bottom surface of the substrate. The package structure also includes an electronic device disposed in the cavity and thermally coupled to the plurality of thermal vias. The package structure further includes a plurality of conductive connectors formed over the electronic device and vertically overlapping the plurality of thermal vias. The package structure also includes an encapsulating material extending from top surfaces of the plurality of conductive connectors to the bottom surface of the cavity. The package structure further includes an insulating layer formed over the encapsulating material and including a redistribution layer structure electrically connected to the electronic device through the plurality of conductive connectors.

A semiconductor device package includes a first substrate extending along a first central plane, and a second substrate electrically connected to the first substrate and extending along a second central plane that is substantially parallel with and offset from the first central plane of the first substrate. One or more capacitors are electrically and mechanically connected to the second substrate via one or more leads. All of the one or more capacitors are positioned at the second substrate. All of the capacitors being positioned at the second substrate, reduces the complexity of and time required to manufacture the semiconductor device package.

A package substrate is provided, in which at least one conductive trace is embedded in an insulating layer having a conductive through via and is electrically connected to the conductive through via, thereby facilitating the manufacture of the conductive trace with ultra-fine line width/line pitch specifications. Therefore, the wiring density can be increased in accordance with the requirements of the product functions.

An IC structure includes a memory stack including a plurality of semiconductor die. The semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface, four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within an upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die. One the semiconductor die includes at least one thermal edge portion exposed from the second sidewall.

A semiconductor structure includes an interposer that includes: a substrate; a redistribution structure (RDS) on the substrate; a passivation film on the RDS, where the passivation film includes a first etch stop layer (ESL) on the RDS and a first dielectric layer on the first ESL; a via embedded in the passivation film, where the via is electrically coupled to a conductive feature of the RDS; a bonding film on the passivation film, where the bonding film includes a second ESL on the passivation film and a second dielectric layer on the second ESL; and a bonding pad and a first dummy bonding pad that are embedded in the bonding film, where the bonding pad is electrically coupled to the via, and the first dummy bonding pad is electrically isolated; and a die attached to the interposer, where a die connector of the die is bonded to the bonding pad.

According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first semiconductor chip and a second semiconductor chip that are bonded along a first direction. The first semiconductor chip may include a first semiconductor layer. The first semiconductor chip may include a plurality of first connection structures extending through the first semiconductor layer along the first direction. A dielectric material may be between and in contact with any two of the first connection structures. The first semiconductor chip and the second semiconductor chip may be coupled by a plurality of first bonding contacts and the plurality of first connection structures. The plurality of first bonding contacts may extend through a first dielectric layer. The first connection structure may be coupled with the first bonding contact.

According to some example embodiments, a semiconductor package includes a first redistribution layer (RDL) including a first redistribution wiring structure, a substrate on the first RDL and including a wiring structure and having a rectangular ring shape, a semiconductor chip on the first RDL and in a space defined by the substrate, a heat dissipation block between the semiconductor chip and the substrate on the first RDL, a molding member on the first RDL and covering sidewalls of the semiconductor chip and the heat dissipation block and an inner sidewall of the substrate, and a second RDL on the semiconductor chip, the heat dissipation block, the substrate and the molding member and including a second redistribution wiring structure. A planar area of the heat dissipation block is greater than a planar of the semiconductor chip.

Provided is a semiconductor package including a first redistribution structure, a second redistribution structure on the first redistribution structure, a first semiconductor device being between the first redistribution structure and the second redistribution structure, a first dummy chip being apart from the first semiconductor device in a lateral direction, a first connection wire being between the first semiconductor device and a first side surface of the first dummy chip, the first connection wire electrically connecting the first redistribution structure to the second redistribution structure, and a second connection wire being on a second side surface opposite to the first side surface of the first dummy chip, the second connection wire electrically connecting the first redistribution structure to the second redistribution structure.

An electronic device and a manufacturing method thereof are disclosed. The manufacturing method of the electronic device includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a through hole penetrating the substrate, a side wall of the through hole connected with the first surface and the second surface; providing a first conductive layer on the substrate, the first conductive layer extending into the through hole; providing a second conductive layer on the first conductive layer, the second conductive layer extending into the through hole and having an original thickness; performing a thinning step to remove at least a portion of the second conductive layer; and performing an inspection step to obtain a first inspection result, and determining whether to continue subsequent steps according to the first inspection result.

An electronic device and a manufacturing method thereof are provided. The electronic device includes a substrate, at least one electronic unit, an adhesive layer, an insulating layer, and a conductive structure. The substrate has at least one recess. The electronic unit is disposed in the recess, and the adhesive layer is disposed between the electronic unit and a bottom surface of the recess. The insulating layer is disposed on the electronic unit and the recess. The conductive structure is disposed on the insulating layer, and the conductive structure penetrates through the insulating layer to be electrically connected to the electronic unit.