H10W76/12

Semiconductor package with gas release holes

A semiconductor package includes a silicon substrate with an active surface and an inactive surface. A semiconductor device, such as an image, light, or optical sensor, is formed in the active surface and disposed on the substrate. A glass plate is coupled to the substrate with adhesive. The glass plate includes a sensor area that corresponds to the area of the semiconductor device and holes through the glass plate that are generally positioned around the sensor area of the glass plate. During formation of the package, the holes through the glass plate allow gas released by the adhesive to escape the package and prevent formation of a gas bubble.

Semiconductor package with gas release holes

A semiconductor package includes a silicon substrate with an active surface and an inactive surface. A semiconductor device, such as an image, light, or optical sensor, is formed in the active surface and disposed on the substrate. A glass plate is coupled to the substrate with adhesive. The glass plate includes a sensor area that corresponds to the area of the semiconductor device and holes through the glass plate that are generally positioned around the sensor area of the glass plate. During formation of the package, the holes through the glass plate allow gas released by the adhesive to escape the package and prevent formation of a gas bubble.

Dam for three-dimensional integrated circuit

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Dam for three-dimensional integrated circuit

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

PACKAGE FOR MULTI-SENSOR CHIP
20260047477 · 2026-02-12 ·

An integrated sensor component includes a chip carrier and a first semiconductor chip and a second semiconductor chip, wherein either both semiconductor chips are arranged on the chip carrier or (alternatively) the second semiconductor chip is arranged on the chip carrier and the first semiconductor chip is arranged on the second semiconductor chip (chip-on-chip). The integrated sensor component further includes a first sensor element integrated in the first semiconductor chip and a second sensor element integrated in the second semiconductor chip, as well as a housing formed by a potting compound, which has an opening. Both the first sensor element and the second sensor element are located within the opening so that they can interact with the atmosphere surrounding the sensor component.

Optical device package preparation method and optical device package

There is provided a semiconductor package. The semiconductor package includes: a semiconductor chip; a mold configured to encapsulate the chip; a redistribution layer; and an optical device electrically connected to the chip through the redistribution layer. The mold is formed with an optical path passing through the mold, and light is input to or output from the optical device through the optical path.

Semiconductor package and method

A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

Semiconductor package with stiffener structure and method of manufacturing the same

A semiconductor package includes a first component, a second component, and a stiffener rib. The first component is disposed on a substrate. The second component is disposed aside the first component and on the substrate. The stiffener rib is disposed between the first component and the second component. The lid is attached to the stiffener rib, the first component and the second component. The lid includes a recess portion on the stiffener rib. A first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib. A first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.

MONOLITHIC SPRING ASSEMBLIES FOR HIGH-FREQUENCY PRESS-PACK MODULES
20260036180 · 2026-02-05 ·

A spring for use in a semiconductor device is provided, which includes a body having a plurality of slits to allow the body to deflect along a first direction; and one or more legs at one or both ends of the body. The plurality of slits are located in a plurality of planes perpendicular to the first direction and distributed along the first direction. The slits in a particular plane of the plurality of planes are interleaved with the slits in an adjacent plane of the plurality of planes

PACKAGE LID ADHESION AND SEAL ENHANCEMENTS

Semiconductor device packages with lids having features for enhanced adhesion and seal to package frames are described. An example package includes a flange having a top surface, a frame integrated with or secured over the top surface of the flange, and a lid secured over the frame. The lid includes a peripheral detent surface extending along a peripheral side surface of the lid in one example. The lid also includes an interference interlock surface extending around an edge of the peripheral detent surface in other examples. The detent surface, interlock surface, and related features help to position and secure the lid over the frame of the package, providing additional surface areas for contact, mechanical interlock, adhesive grip, and other adhesion and sealing mechanisms. The enhancements result in lids that exhibit enhanced adhesion to and seal with package frames, even after temperature cycling.