A method of forming a semiconductor structure includes forming a conductive structure in a first dielectric layer. A second dielectric layer is formed over the first dielectric layer. A conductive contact is formed in the second dielectric layer. The second dielectric layer is etched to form a recess on a top surface of the conductive structure. A native oxide layer is formed on a top surface and a sidewall of the second dielectric layer, the top surface of the conductive structure, and a sidewall of the conductive contact. A first plasma process is performed to form a first material layer over the native oxide layer by using a first plasma gas. A second plasma process is performed to form a second material layer over the first material layer by a second plasma gas different from the first plasma gas. A spacer layer is formed on the second material layer.

A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.

Methods of forming a silicon hardmask are disclosed. In one example, a method may include forming a silicon mask over a device layer, forming a carbon mask over the silicon mask, and forming an opening through the carbon mask. The method may further include forming an oxide layer within the opening by performing an ion implantation process to an upper surface of the silicon mask.

Methods and structures for modulating a metal gate profile include providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers. A liner layer is deposited over surfaces of adjacent semiconductor channel layers of the plurality of semiconductor channel layers. A plasma treatment process is performed to the liner layer. A first portion of the plasma-treated liner layer is removed to form a gap between the adjacent semiconductor channel layers, while a second portion of the plasma-treated liner layer remains disposed on surfaces of the adjacent semiconductor channel layers. After removing the first portion of the plasma-treated liner layer, a gate structure is formed within the gap, where the gate structure has a convex shape or a concave shape.

A microelectronic device including an isolation device with a stabilized dielectric. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a SiO.sub.xN.sub.y surface on the dielectric sidewall of the inorganic dielectric plateau. The SiO.sub.xN.sub.y surface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.

Embodiments of improved process flows and methods are provided to pattern a semiconductor substrate using direct self-assembly (DSA) of metalate salt ionic liquid crystals (ILCs) having metalate anions. After self-assembly of the metalate salt ILCs into ordered structures, an oxidation process is used to remove the organic components of the ordered structures and convert the metalate anions into metal oxide patterns. In addition to providing a robust metal oxide pattern, which can be transferred to the underlying substrate, the process flows and methods disclosed herein enable ILCs to be used as pitch multipliers in advanced patterning techniques.

To enable formation of a film that protects a sidewall of a pattern and is good in film quality, low in etching rate, and good in coverage of the sidewall, a film formation method includes a first step of supplying a gas into a vacuum processing chamber while generating plasma, and forming a film with the generated plasma on a surface of a substrate to be processed, a second step of removing halogen with plasma after the first step, and a third step of oxidizing or nitriding the film with plasma after the second step.

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.