A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

A resistive random access memory array includes a plurality of memory cells. Each memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element. The resistive random access memory array is used to generate physical unclonable function data.

A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

Embodiments of present invention provide a semiconductor device. The semiconductor structure includes a plurality of nanosheet (NS) channel layers having a plurality of source/drain (S/D) regions on sidewalls thereof; and a continuous contact via being in direct contact with the plurality of S/D regions, wherein the continuous contact via has a substantially same horizontal distance to each of the plurality of NS channel layers. A method of manufacturing the same is also provided.

A method of forming a semiconductor device includes: forming a dummy gate structure over a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack over the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings exposes first portions of the first semiconductor material and second portions of the second semiconductor material; recessing the exposed first portions of the first semiconductor material to form sidewall recesses in the first semiconductor material; lining the sidewall recesses with a first dielectric material; depositing a second dielectric material in the sidewall recesses on the first dielectric material; after depositing the second dielectric material, annealing the second dielectric material; and after the annealing, forming source/drain regions in the openings.

A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

A method for fabricating a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a groove exposing different crystal facing a planar surface; depositing a buffer layer over the substrate; epitaxially growing a semiconductor layer over the buffer layer, whereby least a portion of the buffer layer exhibits a cubic crystalline phase structure.