A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes providing a workpiece having a first active region and a second active region protruding from a substrate, lined by cladding layers, and spaced by a first trench. The method also includes forming a dielectric layer over the workpiece to substantially fill the first trench, forming a mask film directly on a portion of the dielectric layer in the first trench after the forming of the dielectric layer, selectively recessing the dielectric layer after the forming of the mask film to form a dummy fin in and protruding from the first trench, performing an etching process to selectively remove the cladding layers to form second trenches, and forming a gate structure over the workpiece to fill the second trenches.

A semiconductor structure includes a channel region over a substrate, a gate structure engaging the channel region, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the channel region, an S/D contact landing on a top surface of the S/D feature, and a dielectric layer disposed on a sidewall of the gate spacer. The S/D feature includes a first layer and a second layer underneath the first layer. The second layer differs from the first layer in composition. The dielectric layer interfaces with both the first layer and the second layer of the S/D feature. In a cross-sectional view along a lengthwise direction of the channel region, a bottommost point of the top surface of the S/D feature is below a top surface of the channel region.

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.

Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.

Techniques for recovering the width of a top gate spacer in a field-effect transistor (FET) device are provided. In one aspect, a FET device includes: at least one gate; source/drain regions present on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source/drain regions, wherein each of the gate spacers includes an L-shaped spacer alongside the at least one gate and a dielectric liner disposed on the L-shaped spacer; and at least one channel interconnecting the source/drain regions. A method of forming a FET device is also provided which includes recovering the width of the top gate spacer using the dielectric liner.

Multigate devices and methods for fabricating such are disclosed herein. An exemplary multigate device includes a first FET disposed in a first region; and a second FET disposed in a second region of a substrate. The first FET includes first channel layers disposed over the substrate, and a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers. The second FET includes second channel layers disposed over the substrate, and a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers. A number of the first channel layers is greater than a number of the second channel layers. A bottommost one of the first channel layers is below a bottommost one of the second channel layers.