A planar gate transistor device, comprising a semiconductor substrate and a conductive gate electrode formed over the semiconductor substrate. A conductive split gate electrode is formed over the semiconductor substrate proximate a side of the conductive gate electrode near a drain contact and a conductive contact plug is formed over the split gate electrode.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second transistor separated by a single diffusion break; and a source/drain contact to a source/drain region of the first transistor, the source/drain region being next to the single diffusion break, where the source/drain contact has an L-shape having a vertical portion on top of a horizontal portion, the horizontal portion extending at least partially into a sidewall spacer at a sidewall of the single diffusion break. A method of forming the same is also provided.

According to some example embodiments, an integrated circuit includes a first inter-wiring insulating film on a substrate, a first and second wiring patterns spaced apart from each other on the first inter-wiring insulating film, a first etch stop layer on the first inter-wiring insulating film, the first and second wiring patterns, and a second inter-wiring insulating film on the first etch stop layer. Each of the first and second wiring patterns includes a first lower pattern in the first inter-wiring insulating film, and a first upper pattern on an upper surface of the first inter-wiring insulating film. The first etch stop layer extends along profiles of the upper surface of the first inter-wiring insulating film, and a side face and an upper surface of the first upper pattern. The second inter-wiring insulating film defines a first void between the first wiring pattern and the second wiring pattern.

An apparatus includes a through-silicon via (TSV) including a conductive material; a first contact plug having an upper surface and a bottom surface directly connected to an upper surface of the TSV; a first wiring directly connected to the upper surface of the first contact plug; a second wiring having an upper surface; a second contact plug having an upper surface and a bottom surface directly connected to the upper surface of the second wiring; and a third wiring directly connected to the upper surface of the second contact plug; wherein the first wiring and the third wiring are in a substantially same level.

An integrated circuit comprising: a plurality of devices arranged on a front side of a substrate; a first backside pattern and a second backside pattern, wherein the first backside pattern and the second backside pattern extend in a first direction along a first track in a first backside wiring layer, wherein the first backside wiring layer is on a back side of the substrate, and wherein the first backside pattern and the second backside pattern are configured to receive a first supply voltage and provide the first supply voltage to at least one of the plurality of devices; and a third backside pattern extending in the first direction along the first track between the first backside pattern and the second backside pattern, in the first backside wiring layer, wherein the third backside pattern is configured to receive a source supply voltage and provide the source supply voltage to a first device of the plurality of devices.

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, a first dielectric layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The first dielectric layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, a first dielectric layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The first dielectric layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

A memory structure including a storage transistor having a data storage storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor being configurable to have a threshold voltage that is representative of data stored in the data storage region; a word line electrically connected to the gate terminal, configured to provide a control voltage during a read operation; a bit line electrically connecting the first drain or source terminal to data detection circuitry; and a source line electrically connected to the second drain or source terminal, configured to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.