Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.

Provided is a technique for enhancing the accuracy of deterioration diagnosis in a semiconductor device. The semiconductor device relating to the technique disclosed in the present specification is provided with a case, a semiconductor chip inside the case, a metal wire bonded to an upper surface of the semiconductor chip, at least one test piece inside the case, and a pair of terminals provided outside the case and connected to the test piece. The test piece is separated from the metal wire inside the case.

A capacitor module includes a first die and a second die. Each of the first die and the second die includes a capacitor device and a circuit structure electrically connected to the capacitor device. The circuit structure includes a pad and a first signal line. The first signal line includes a first pad connection portion and a first signal transmission portion. The first pad connection portion is located below the pad and is electrically connected to the pad. The first signal transmission portion is electrically connected to the capacitor device. The first signal line of the first die further includes first fuses connecting the first pad connection portion and the first signal transmission portion. The first signal line of the second die is broken, so that the first pad connection portion of the second die is electrically separated from the first signal transmission portion.

An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.

The invention provides a semiconductor testkey, which includes a testkey on a substrate, the testkey includes a first resistor pattern, a second resistor pattern and a third resistor pattern arranged in a strip, the distance between the first resistor pattern and the second resistor pattern is defined as a first distance, and the distance between the second resistor pattern and the third resistor pattern is defined as a second distance, the first resistor pattern, the second resistor pattern and the third resistor pattern have the same pattern, and the second distance is larger than the first distance.

A semiconductor system, a semiconductor device, a through-silicon via (TSV) test method, and a method of manufacturing a semiconductor device are provided. The semiconductor system includes a semiconductor device including a buffer die and first to L-th (where L is an integer greater than or equal to 2) stack dies stacked on the buffer die and communicating with the buffer die through N (where N is a positive integer) TSVs; and a TSV test device that measures each of voltages at one end and voltages at another end on the N TSVs according to a clock signal, compares each of the voltages at the one end and the voltages at the other end with a reference voltage, and determines whether each of the N TSVs has a plurality of TSV defect types according to comparison results.

Electrostatic discharge (ESD) test systems include a FET-based pulse generator using pairs of back-to-back FETs coupled to produce an ESD pulse based on discharging a capacitor that is coupled in series with a device under test (DUT). A number of FETs can be selected based on an intended ESD test voltage magnitude.

A semiconductor package may include a first semiconductor die having a first width; a second semiconductor die on the first semiconductor die, the second semiconductor die having a second width that is smaller than the first width; and a mold layer at least partially covering a side surface of the second semiconductor die, and a top surface of the first semiconductor die, wherein the first semiconductor die comprises at least one first detection pattern, the at least one first detection pattern being on the top surface of the first semiconductor die and in contact with a bottom surface of the mold layer.

An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device. An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device composed of thermoelectric elements and at least one switch to disconnect at least one thermoelectric element from the thermoelectric device. Methods for testing embedded thermoelectric devices.

A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.