A semiconductor device includes an integrated circuit having a first resistor configuring a voltage divider circuit, a sensing resistor configured to measure a sheet resistance having a same attribute as that of the first resistor, a temperature detection circuit configured to detect a value of a first temperature, a storage circuit configured to store a table including first information for each of a plurality of values of the first temperatures, the first information corresponding to a sheet resistance of the first resistor obtained based on a result of measurement of the sensing resistor, and indicating a relationship between a second temperature and a divided voltage of the voltage divider circuit at the second temperature, and an arithmetic circuit configured to obtain the second temperature, based on the first information at the value of the first temperature detected by the temperature detection circuit and the divided voltage.

A standby current detection circuit includes multiple first transistors. The first transistors are coupled in series to form a first detection circuit string, where N is a positive integer. The first detection circuit string is disposed on a scribe lane of a wafer, and the first detection circuit string is operated in a standby state and serves as a test medium for a standby current.

An example integrated circuit includes a plurality of cells positioned in a plurality of rows extending in a first horizontal direction. The plurality of cells include a first cell disposed in a first row. The first cell comprises a first active pattern extending in the first horizontal direction and a first backside pattern overlapping the first active pattern in a vertical direction and extending in the first horizontal direction in a first backside wiring layer below the first active pattern. The first backside pattern is removed from a first inspection region that overlaps the first active pattern and extends in a second horizontal direction.

An electronic product includes a number of die and an interposer. The die are coupled to the interposer. Each respective die includes an edge integrity detection structure extending along at least part of an edge of the respective die. The interposer includes at least one pad coupled to at least one edge integrity detection structure of the die.

A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

An electronic product includes a package substrate, a number of die, and an interposer. The die are coupled to the interposer, and each respective includes an edge integrity detection structure extending along at least part of an edge of the respective die. The package substrate includes at least one pad coupled to at least one edge integrity detection structure of at least one die of the die.

A wafer test probe includes a pillar, a conductive line isolated from and extending through the pillar, a probe tip forming an opening, and a first conductive coating isolated from the pillar to coat the probe tip at least at the opening. The probe time includes blade features disposed in electrical contact with the conductive line via the first conductive coating. The blade features terminate at the opening and are configured to conductively penetrate a solder bump. A second conductive coating is disposed over the first conductive coating to coat the blade features.

A method includes bonding a second die including second feature to a first die. The first die includes a first feature. A first image of at least a portion of the first die is captured using a first image sensor disposed at a first angle that is normal to the first surface. A second image of at least a portion of the second die is captured using a second image sensor disposed at a second angle. The first and second images include at least a portion of the first feature and the second feature. At least one offset between the features are determined based on the first image and the second image. An alignment correction between the dies are determined based on the offset. One or more alignment commands are sent based on the alignment correction to a robot end effector system of an optical inspection system.

A surface scanning tool and methods of using a surface scanning tool to determine a surface shape of a tool. In embodiments, the surface scanning tool includes a laser, a detector, and a signal analysis module. The laser sends a beam of light that is reflected off a bottom surface of the tool. The detector receives the reflected beam of light and sends the reflected beam of light signals to a signal analysis module. The signal analysis module determines a surface shape of the bottom surface and triggers mitigation actions. In alternative embodiments, the surface scanning tool includes a camera and a signal analysis module. The camera takes a picture of the bottom surface of the tool and sends the image to the signal analysis module. The signal analysis module determines the surface shape of the bottom surface and triggers mitigation actions.

A semiconductor wafer is diced along a plurality of dicing lines in a first direction and a second direction different from the first direction so that a chip is cut out from an effective area. The semiconductor water includes a film formation pattern. At least one dicing line included in the plurality of dicing lines is an on-pattern dicing line which overlaps the film formation pattern in its entire or partial length.