A semiconductor device package includes a first substrate extending along a first central plane, and a second substrate electrically connected to the first substrate and extending along a second central plane that is substantially parallel with and offset from the first central plane of the first substrate. One or more capacitors are electrically and mechanically connected to the second substrate via one or more leads. All of the one or more capacitors are positioned at the second substrate. All of the capacitors being positioned at the second substrate, reduces the complexity of and time required to manufacture the semiconductor device package.

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m; and electrically connecting the first landing pad to one of the two electrodes.

A method includes forming a first electrode layer having a first opening, with the first opening having a first lateral dimension, forming a first capacitor insulator over the first electrode layer, and forming a second electrode layer over the first capacitor insulator, with the second electrode layer having a second opening. The first opening is directly underlying the second opening. The second opening has a second lateral dimension greater than the first lateral dimension. The method further includes depositing a dielectric layer over the second electrode layer, and forming a contact opening, which comprises a first portion including the first opening, and a second portion including the second opening. A conductive plug is formed in the contact opening.

A semiconductor die includes semiconductor devices located on a semiconductor substrate, metal-insulator-metal corner structures overlying the semiconductor devices and located in corner regions of the semiconductor die. Metal-insulator-metal corner structures are located in the corner regions of the semiconductor die. Each of the metal-insulator-metal corner structures has a horizontal cross-sectional shape selected from a triangular shape and a polygonal shape including a pair of laterally-extending strips extending along two horizontal directions that are perpendicular to each other and connected to each other by a connecting shape.

The present disclosure relates to a semiconductor package, and a semiconductor package according to an embodiment includes: a first redistribution layer including a first redistribution pattern, through which a hole penetrates, a semiconductor chip disposed on the first redistribution layer, a first conductive pad disposed on a bottom surface of the first redistribution layer, and a passive device connected to the first conductive pad. A first part of the first conductive pad overlaps the hole with respect to a top down view, and the remaining part of the first conductive pad overlaps a peripheral portion of the first redistribution pattern on a plane. The peripheral portion surrounds the hole with respect to a top down view.

A glass layer having a first surface and a second surface opposing each other in a first direction; a plurality of conductive through-vias penetrating at least a portion of the glass layer between the first surface and the second surface; and a capacitor member including a plurality of conductive electrodes each penetrating at least a portion of the glass layer between the first surface and the second surface. At least a portion of the plurality of conductive electrodes has regions overlapping each other in a second direction perpendicular to the first direction.

Disclosed are power modules with vertically-oriented power dies. A power die includes a power transistor. A plane of the power die is oriented vertically relative to a plane of a motherboard or other substrate. An inductor is disposed on a top end of the power module or between two power dies in the power module.

A semiconductor structure includes a core layer; a passive component disposed within the core layer; and a first redistribution layer disposed over the core layer, wherein the first redistribution layer includes a first interconnect, a second interconnect, and a third interconnect disposed between and electrically isolated from the first interconnect and the second interconnect. The third interconnect is electrically connected to the passive component, and at least one of the first interconnect and the second interconnect is electrically isolated from the passive component. A method of manufacturing the semiconductor structure includes providing a first bias between the first interconnect and the second interconnect, providing a second bias to the passive component through the third interconnect, wherein the first bias is greater than the second bias.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature.