A power module includes: a first substrate having an outer surface and an inner surface; a semiconductor die coupled to the inner surface of the first substrate; a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate; and a flex circuit coupled to the semiconductor die.

Chip packages, electronic devices and method for making the same are described herein. The chip packages and electronic devices have a heat spreader disposed over a plurality of integrated circuit (IC) devices. The heat spreader has an opening through which a protrusion from an overlaying cover extends into contact with one or more of the IC devices to provide a direct heat transfer path to the cover. Another one or more other IC devices have a heat transfer path to the cover through the heat spreader. The separate heat transfer paths allow more effective thermal management of the IC devices of the chip package.

In one example, an electronic device, comprises a substrate comprising a dielectric structure and a conductive structure, an electronic component over a top side of the substrate, wherein the electronic component is coupled with the conductive structure; an encapsulant over the top side of the substrate and contacting a lateral side of the electronic component, wherein the encapsulant comprises a first trench on a top side of the encapsulant adjacent to the electronic component, a lid over the top side of the encapsulant and covering the electronic component; and an interface material between the top side of the encapsulant and the lid, and in the first trench. Other examples and related methods are also disclosed herein.

A semiconductor module includes a heat sink configured to conduct a cooling fluid in a cooling-fluid flow direction. A first semiconductor assembly is arranged on a surface of the heat sink. The first semiconductor assembly includes a first substrate having a first dielectric material layer, and a first semiconductor element connected to the first substrate. A second semiconductor assembly is arranged on the surface of the heat sink and closest to a downstream end of the heat sink. The second semiconductor assembly includes a second substrate having a second dielectric material layer, and a second semiconductor element connected to the second substrate. The second dielectric material layer has a thermal conductivity which is higher than a thermal conductivity of the first dielectric material layer.

A semiconductor device includes a heat sink, a base material including an insulating layer and mounted on the heat sink on one side in a first direction, a first conductive layer bonded to the base material and located on a side opposite the heat sink with respect to the base material, a first semiconductor element bonded to the first conductive layer, a first power terminal electrically connected to the first conductive layer and the first semiconductor element, and a sealing resin covering the first conductive layer and the first semiconductor element. The first power terminal is exposed from the sealing resin. The first power terminal is surrounded by a peripheral edge of the sealing resin as viewed in the first direction.

A semiconductor package assembly, comprising: a semiconductor package comprising: a semiconductor die mounted on a substrate; a pair of interconnection blocks mounted at opposite sides of the semiconductor die; and an encapsulant layer, wherein the pair of interconnection blocks have respective top surfaces exposed and a top surface of the semiconductor die is exposed; and an inductor block mounted on the semiconductor package, comprising: an inductor extending through the insulation body in a horizontal direction, and having a pair of inductor contact pads exposed at a bottom surface of the insulation body, wherein the pair of inductor contact pads are aligned to and electrically coupled to the pair of interconnection blocks; and a thermally conductive coating formed at an outer surface of the insulation body and extending in a vertical direction of the insulation body from the bottom surface to a top surface of the insulation body.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

A pin fin placement assembly utilized to form pin fins in a thermal dissipating feature is provided. The pin fin placement assembly may place the pin fins on an IC die disposed in the IC package. The pin fin placement assembly may assist massively placing the pin fins with desired profiles and numbers on desired locations of the IC die. The plurality of pin fins is formed in a first plurality of apertures in the pin fin placement assembly. A thermal process is then performed to solder the plurality of pin fins on the IC die.

In a method for producing a semiconductor module, a heatsink is produced from a first metal material and a cavity with a base surface and a wall portion is introduced in a heatsink surface such as to form an obtuse angle between the base surface and the wall portion. In addition, a depression is introduced into the base surface of the cavity which depression is smaller than the base surface of the cavity. A second metal material is applied in the cavity and the depression using a thermal spraying method to form a heat-spreading layer of different thicknesses, with the second metal material having a thermal conductivity which is higher than a thermal conductivity of the first metal material. A semiconductor arrangement is connected to the heat-spreading layer.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.