H10P52/402

Surface treatment composition, surface treatment method, and method for producing semiconductor substrate

Provided is a means for sufficiently removing residues remaining on the surface of a polished object and reducing the surface roughness of the polished object. The present invention relates to a surface treatment composition containing components (A) to (C), and having pH of more than 7.0: the component (A): a cyclic amine compound having a nitrogen-containing non-aromatic heterocyclic ring, the component (B): a nonionic polymer, the component (C): a buffer represented by a formula: A-COO.sup.NH.sub.4.sup.+ wherein A is an alkyl group having from 1 to 10 carbon atoms, or a phenyl group.

SYSTEM AND A METHOD FOR CHEMICAL MECHANICAL PLANARIZATION OF a-Si AND SiO2
20260085219 · 2026-03-26 ·

Systems and methods are provided for chemical mechanical planarization a-Si and SiO.sub.2 substrates. The polishing composition is acidic and includes a morpholine compound including a heteroatom substituent at a nitrogen atom of the morpholine compound, and an abrasive. The polishing composition non-selectively removes both a-Si and SiO.sub.2.

METHOD FOR THINNING A COMPOSITE STRUCTURE CARRIED BY A POLYCRYSTALLINE SIC CARRIER SUBSTRATE, WITH REDUCED WARPAGE
20260090307 · 2026-03-26 ·

A method of processing a composite structure including a thin layer of single-crystal silicon carbide disposed on a polycrystalline silicon carbide carrier substrate, includes, after formation of electronic component elements on a front face of the composite structure, grinding a rear face of the composite structure and removing a work-hardened layer present on the surface of the rear face as a result of the grinding process.

SILICON WAFER WITH LASER MARK AND MANUFACTURING METHOD OF THE SAME
20260090298 · 2026-03-26 · ·

In order to have uniform dot holes even when a deep laser mark of approximately 100 m depth is formed, a silicon wafer having a crystal plane orientation of (100) has an identification mark configured by a plurality of dot holes on a surface with a surface roughness of 0.15 to 0.60 nm. A ratio between a length in a <100> direction and a length in a <110> direction of an opening of the dot hole on a wafer surface is 1 to 1.10, the length in the <100> direction of the opening is 80 m to 110 m, a depth of the dot hole in a cross-section is 80 m to 110 m, and a bottom surface of the dot hole is a flat surface of a (100) plane.

Chemical mechanical polishing compositions and methods of use thereof

A polishing composition includes at least one abrasive, at least one organic acid, at least one anionic surfactant comprising at least a phosphate, at least one phosphonic acid compound having a molecular weight below 500 g/mol, at least one azole containing compound, at least one alkylamine compound having a 6-24 carbon alkyl chain, and an aqueous solvent, and optionally, a pH adjuster.

Chemical planarization

Examples are disclosed that relate to planarizing substrates without use of an abrasive. One example provides a method of chemically planarizing a substrate, the method comprising introducing an abrasive-free planarization solution onto a porous pad, contacting the substrate with the porous pad while moving the porous pad and substrate relative to one another such that higher portions of the substrate contact the porous pad and lower portions of the substrate do not contact the porous pad, and removing material from the higher portions of the substrate via contact with the porous pad to reduce a height of the higher portions of the substrate relative to the lower portions of the substrate.

Platen rotation device

A method includes controlling a rotational kinetic energy of a rotor assembly of a wafer-platen, wherein a rotational velocity of the wafer-platen is either increased or decreased. The method further includes generating an electrical energy output of the wafer-platen based on decreased rotational kinetic energy of the wafer-platen. The method further includes storing the electrical energy output by the rotator assembly based on the decreased rotational kinetic energy of the wafer-platen.

Hard mask removal method

A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Polishing composition, polishing method, and method for producing polished substrate
12590225 · 2026-03-31 · ·

According to the present invention, a moderately high polishing speed for a specific material and appropriate ratio of polishing speeds between two or more different materials are achieved in polishing using a polishing composition. The present invention relates to a polishing composition comprising abrasive grains, a water-soluble polymer having no alcoholic hydroxyl group in a side chain, a polyvalent carboxylic acid (salt), and an oxidizing agent, and having a pH of less than 6.

Apparatus and method for manufacturing semiconductor structure

An apparatus and a method for forming a semiconductor structure are provided. The apparatus includes a polishing pad, a polishing head and a temperature control module. The polishing head mounts a substrate against the polishing pad. The temperature control module faces the polishing pad. The temperature control module includes a first temperature controller and a second temperature controller. The first temperature controller is configured to control a first temperature of a first zone of the polishing pad. The second temperature controller is configured to control a second temperature of a second zone of the polishing pad.