The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a plurality of nanostructures over a substrate, depositing a dielectric layer to wrap around the plurality of nanostructures, forming a mask layer over the dielectric layer, etching back the mask layer such that a top surface of the mask layer is coplanar with or lower than a top surface of a topmost nanostructure of the plurality of nanostructures, performing a treatment to reduce a thickness of the topmost nanostructure of the plurality of nanostructures, after the performing of the treatment, selectively removing the mask layer, and forming a gate electrode over the insulation layer and the dielectric layer to wrap around the plurality of nanostructures.

Provided is a method of forming a thin film to minimize an increase in defects at an interface during a high-temperature oxidation process of a SiC substrate. The method includes depositing a first thin film on the SiC substrate by applying a radical gas, forming an oxide film on the first thin film by performing the high-temperature oxidation process, and performing annealing on the oxide film.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

This disclosure relates to a semiconductor structure (100), comprising a crystalline silicon substrate (110), having a surface (111), and a crystalline silicon oxide superstructure (120) on the surface (111) of the silicon substrate (110), the silicon oxide superstructure (120) having a thickness of at least two molecular layers and a (11) plane structure using Wood's notation.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.