A method for manufacturing a semiconductor device includes: forming a semiconductor structure on a semiconductor substrate, the semiconductor structure including first and second source/drain regions disposed on the semiconductor substrate in a first direction and spaced apart from each other in a second direction transverse to the first direction, and a plurality of channel features disposed between and connected to the first and second source/drain regions and spaced apart from one another in the first direction; forming an interfacial material layer to cover the channel features; forming a metal oxide layer on the interfacial material layer; converting a portion of the interfacial material layer into a metal silicate layer so as to form a plurality of interfacial features respectively covering the channel features, the metal silicate layer being formed between the metal oxide layer and the interfacial features; and removing the metal oxide layer and the metal silicate layer.

The present application provides a method for improving continuity of a work function thin film, forming a tunneling oxide layer on a substrate; forming an isolation layer on the tunneling oxide layer; forming a work function thin film on the isolation layer, the work function thin film serves as a floating gate in a semi-floating gate device to store charges and conduction electrons, performing a heat treatment on the tunneling oxide layer, the isolation layer and the work function layer, the isolation layer reacts with a surface of the tunneling oxide layer to form a dense barrier layer, the isolation layer reacts with O in the tunneling oxide layer to form a new tunneling oxide layer, the heat treatment lasts until the isolation layer is fully consumed, and the work function thin film remaining after the reaction uniformly covers an upper surface of the dense barrier layer.

There is provided a diode including an anode electrode provided on a side of a front surface of a semiconductor substrate, an interlayer dielectric film disposed between the semiconductor substrate and the anode electrode, a first anode region of a first conductivity type provided on the front surface of the semiconductor substrate, a second anode region of a second conductivity type, which is different from the first conductivity type, provided on the front surface of the semiconductor substrate, a first contact hole provided in the interlayer dielectric film, causing the anode electrode to be in Schottky contact with the first anode region, and a second contact hole provided in the interlayer dielectric film and different from the first contact hole, causing the anode electrode to be in ohmic contact with the second anode region.

In embodiments of the present disclosure, enhanced nanoribbons of GAA FETs are formed using a high-temperature diffusion process before the source/drain regions are formed. The diffusion process includes forming an additive material layer (e.g., comprising germanium) around crystalline nanoribbons (e.g., comprising purely or predominantly silicon), forming a capping layer around the additive material layer, diffusing the additive material into the crystalline nanoribbons (e.g., via heating), and removing the capping layer.

A semiconductor structure includes: a semiconductor substrate; a gate dielectric layer over the semiconductor substrate; and a gate electrode over the gate dielectric layer. The gate dielectric layer includes a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion includes a third portion including nitrogen and enclosed by the first portion.

Multigate devices having bottom insulation and methods of fabrication thereof are disclosed. An exemplary method includes forming a first source/drain recess in a first device region, forming a second source/drain recess in a second device region, forming a first source/drain structure in the first source/drain recess, and forming a second source/drain structure in the second source/drain recess. Forming the second source/drain structure includes forming an insulator layer in the second source/drain recess, forming a mask over the first source/drain structure after performing a first nitrogen thermal treatment on the insulator layer, and forming a doped semiconductor layer over the insulator layer after performing a second nitrogen thermal treatment on the mask. The first nitrogen thermal treatment may increase a thickness and/or reduce an etch rate of the insulator layer. The first device region may be a p-type transistor region, and the second device region may be an n-type transistor region.