The present disclosure provides a semiconductor device package. The semiconductor device package includes a first antenna pattern disposed at a first elevation and a second antenna pattern disposed at a second elevation different from the first elevation. The first antenna pattern and the second antenna pattern define an air cavity. The semiconductor device package also includes a circuit layer. The air cavity is between the first antenna pattern, the second antenna pattern, and the circuit layer.

The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

The present invention provides a package including a first pad, a die and at least one package ESD component is disclosed. The first pad is configured to receive a signal from a device external to the package. The die comprises a second pad and an internal circuit, wherein the internal circuit is configured to receive the signal from the first pad via the second pad. The at least one ESD component is positioned outside the die.

An antenna apparatus includes an antenna substrate with opposite first and second surfaces; and a PCB having opposite first and second surfaces. Antenna elements are disposed at the first surface of the antenna substrate. Electrically conductive columns, each having a first end attached to the second surface of the PCB and a second end attached to the second surface of the antenna substrate, secure the PCB to the antenna substrate and provide an electrical interconnect between the PCB and the antenna substrate. RFIC chips are each attached to the second surface of the antenna substrate and are coupled to the antenna elements. At least one circuit element is attached to the first surface of the PCB and electrically coupled to at least one of the RFIC chips through at least one of the electrically conductive columns.

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One stacked die platform includes a substrate, a first die and a second die stacked together, and first and C2C interfaces on the first and second dies, respectively. The stacked die platform also includes switching circuitry and a link monitoring unit. The switching circuitry is configured to selectively connect either the first C2C interface or the second C2C interface to the bump connections, where only one of the first C2C interface and the second C2C interface is active at a time. The link monitoring unit is configured to monitor link status and control operation of the switching circuitry to provide redundancy for C2C communication failures.

Disclosed herein are devices, systems, and methods related to edge couplers for providing wireless channel interconnects between edges of chiplets, components, modules, devices, packages, SoCs, etc. Such edge couplers may be formed from a stack of multiple layers and a core arranged between layers of the stack. A driven via extends from at least one feed layer of the stack of multiple layers into the core, wherein the driven via is isolated from ground. A plurality of grounded through-hole vias are grounded, extend from at least one ground layer of the stack, and traverse through the core, wherein the plurality of grounded through-hole vias partially surround the driven via.

A semiconductor device has a first substrate. A first semiconductor die and second semiconductor die are disposed over the substrate. An interconnect bridge is disposed over the first semiconductor die and second semiconductor die. The interconnect bridge has a second substrate. A conductive trace is formed over the second substrate. The conductive trace is electrically coupled from the first semiconductor die to the second semiconductor die. An IPD is also formed over the second substrate. The IPD is electrically coupled between the first semiconductor die and second semiconductor die. An encapsulant is deposited over the first substrate, first semiconductor die, second semiconductor die, and interconnect bridge.

Aspects and embodiments disclosed herein include a stacked power amplifier cell comprising an active diffusion layer deposited on a substrate, a first series transistor including a first source electrode, a first drain electrode, and a first gate contact mounted on the active diffusion layer, and a second series transistor including a second source electrode, a second drain electrode, and a second gate contact mounted on the active diffusion layer, the second source electrode being electrically connected to the first drain electrode and a thickness of the second gate oxide layer being greater than a thickness of the first gate oxide layer.

A flip-chip bonding-based antenna packaging structure and its manufacturing method are provided. The flip-chip bonding-based antenna packaging structure includes a lead frame structure and a redistribution structure disposed above the lead frame structure. The redistribution structure includes a first surface and a second surface. The lead frame structure is disposed on the redistribution structure and includes a metal member, a first active element, and a passive element. The metal member includes a base portion, a first supporting portion on the base portion, and an extension portion adjacent to the first supporting portion. The extension portion extends from the base portion, and the first supporting portion is parallel to the extension portion. The first active element is disposed between the first supporting portion and the first surface. The passive element is disposed on the second surface and is electrically connected to the first active element.

Aspects of the disclosure advantageously provide circuits and methods using the same in signal transmission. In some embodiments, a circuit includes a signal transmission line configured to transmit a signal between two ports, the signal transmission line comprising a first transmit portion coupled to a second transmit portion via a first interconnect stage and the second transmit portion coupled to a third transmit portion via a second interconnect stage, wherein the second transmit portion comprises a quarter wavelength transmission line having a length that is a quarter of a wavelength of the signal being transmitted between the two ports. In some embodiments, the first interconnect stage and the second interconnect stage each comprise a contact pad having identical, or substantially similar, shape and size.